{ "updated": "2026-10-22", "precisions": [ { "key": "fp64", "label": "FP64", "unit": "TFLOPS", "tensor": false, "desc": "Double precision on the regular CUDA cores (scientific computing)." }, { "key": "fp64tc", "label": "FP64 TC", "unit": "TFLOPS", "tensor": false, "desc": "Double precision on tensor cores. Only big data-centre chips (A100, H100, B200 class) have these." }, { "key": "fp32", "label": "FP32", "unit": "TFLOPS", "tensor": false, "desc": "Single precision on the regular CUDA cores (no tensor cores)." }, { "key": "tf32", "label": "TF32", "unit": "TFLOPS", "tensor": true, "desc": "FP32 matmuls on tensor cores with a 10-bit mantissa (PyTorch's 'high' matmul precision)." }, { "key": "fp16", "label": "FP16", "unit": "TFLOPS", "tensor": true, "desc": "Half precision on tensor cores, summed in FP32 (PyTorch's default). Switch to 'FP16 accumulate' for NVIDIA's GeForce headline rate." }, { "key": "bf16", "label": "BF16", "unit": "TFLOPS", "tensor": true, "desc": "bfloat16 on tensor cores (always summed in FP32). What most training uses." }, { "key": "fp8", "label": "FP8", "unit": "TFLOPS", "tensor": true, "desc": "8-bit floats on tensor cores (Ada, Hopper and newer), summed in FP32." }, { "key": "fp6", "label": "FP6", "unit": "TFLOPS", "tensor": true, "desc": "6-bit floats on tensor cores (Blackwell and newer)." }, { "key": "fp4", "label": "FP4", "unit": "TFLOPS", "tensor": true, "desc": "4-bit floats (NVFP4/MXFP4) on tensor cores (Blackwell and newer)." }, { "key": "int8", "label": "INT8", "unit": "TOPS", "tensor": true, "desc": "8-bit integers on tensor cores." }, { "key": "int4", "label": "INT4", "unit": "TOPS", "tensor": true, "desc": "4-bit integers on tensor cores (Turing, Ampere and Ada only)." } ], "cards": [ { "id": "rubin-hgx-nvl8", "name": "NVIDIA Rubin (HGX NVL8, per GPU)", "short": "Rubin HGX", "seg": "datacenter", "arch": "Rubin", "archGroup": "Rubin", "cls": "rubin", "clsLabel": "Rubin", "chip": null, "date": "2026-01", "t": 2026.0, "status": null, "ff": "SXM (HGX 8-GPU baseboard with x86 host or single-socket Vera CPU)", "mem": 288.0, "memType": "HBM4", "bw": 22000.0, "tdp": null, "sms": 224.0, "tc": 896.0, "cuda": null, "boost": null, "v": { "fp32": [ 130.0, null, "p" ], "fp64": [ 33.0, null, "p" ], "tf32": [ 2000.0, 4000.0, "p" ], "fp16": [ 4000.0, 8000.0, "p" ], "bf16": [ 4000.0, 8000.0, "p" ], "fp8": [ 17500.0, 35000.0, "p" ], "fp6": [ 17500.0, 35000.0, "p" ], "fp4": [ 35000.0, 50000.0, "p" ], "int8": [ 250.0, 500.0, "p" ] }, "how": { "fp32": "NVIDIA: “NVIDIA Rubin GPU: FP32 130 TFLOPS” [nvidia.com]", "fp64": "NVIDIA: “NVIDIA Rubin GPU: FP64 33 TFLOPS” [nvidia.com]", "tf32": "NVIDIA: “NVIDIA Rubin GPU: TF32² 2 PFLOPS” [nvidia.com]", "fp16": "NVIDIA: “NVIDIA Rubin GPU: FP16/BF16² 4 PFLOPS” [nvidia.com]", "bf16": "NVIDIA: “NVIDIA Rubin GPU: FP16/BF16² 4 PFLOPS” [nvidia.com]", "fp8": "NVIDIA: “NVIDIA Rubin GPU: FP8/FP6 Training² 17.5 PFLOPS” [nvidia.com]", "fp6": "NVIDIA: “NVIDIA Rubin GPU: FP8/FP6 Training² 17.5 PFLOPS” [nvidia.com]", "fp4": "NVIDIA: “Individual GPU Specifications, NVIDIA Rubin GPU¹: NVFP4 Inference 50 PFLOPS; NVFP4 Training² 35 PFLOPS (¹Sparse specification. ²Dense specification.)” [nvidia.com]", "int8": "NVIDIA: “NVIDIA Rubin GPU: INT8² 250 TOPS” [nvidia.com]" }, "na": { "fp64tc": "NVIDIA doesn't publish this figure", "int4": "NVIDIA doesn't publish this figure" }, "headline": null, "anchor": null, "notes": "The per-GPU table on nvidia.com/hgx has the same compute figures as the NVL72 per-GPU column, but lists 22 TB/s HBM4 and 3.6 TB/s NVLink. Its '¹' (sparse) marker sits on the column header, not on the NVFP4 Inference row. Conflict with the same page's HGX Rubin NVL8 system table (8 GPUs; identical in the Oct26 Vera Rubin datasheet): NVFP4 inference 400 PFLOPS (sparse), NVFP4 training 270, FP8/FP6 training 130, FP16/BF16 32 PFLOPS, TF32 '16 POPS' (sic; datasheet: 16 PFLOPS), FP32 1,040 TFLOPS, FP64 265 TFLOPS, 2 TB HBM4 | 130 TB/s. Per GPU that is 50 / 33.75 / 16.25 / 4 / 2 PFLOPS, 130 / 33.1 TFLOPS, 250 GB and 16.25 TB/s. The DGX Rubin NVL8 datasheet (Sep26, 'Preliminary information') instead gives 400 PFLOPS NVFP4 inference, 280 PFLOPS NVFP4 training and 140 PFLOPS FP8/FP6 training (dense), 2.3 TB and 176 TB/s (= 50 / 35 / 17.5 PFLOPS, 287.5 GB, 22 TB/s per GPU), ~24 kW, NVLink 28.8 TB/s total. No per-GPU TDP or clocks are published.", "sources": [ { "t": "nvidia.com — /en-us/data-center/hgx/", "u": "https://www.nvidia.com/en-us/data-center/hgx/" }, { "t": "dam-cdn.nvd.orangelogic.com — /AssetLink/56p68o47y6f1yucpubl0ump1c0aif422.pdf", "u": "https://dam-cdn.nvd.orangelogic.com/AssetLink/56p68o47y6f1yucpubl0ump1c0aif422.pdf" }, { "t": "dam-cdn.nvd.orangelogic.com — /AssetLink/3i7x83r03804oi762knft3d4l382r05x.pdf", "u": "https://dam-cdn.nvd.orangelogic.com/AssetLink/3i7x83r03804oi762knft3d4l382r05x.pdf" }, { "t": "developer.nvidia.com — /blog/inside-nvidia-rubin-gpu-architecture-powering-the-era-of-agentic-ai/", "u": "https://developer.nvidia.com/blog/inside-nvidia-rubin-gpu-architecture-powering-the-era-of-agentic-ai/" } ], "aka": null }, { "id": "rubin-nvl72", "name": "NVIDIA Rubin (Vera Rubin NVL72, per GPU)", "short": "Rubin NVL72", "seg": "datacenter", "arch": "Rubin", "archGroup": "Rubin", "cls": "rubin", "clsLabel": "Rubin", "chip": null, "date": "2026-01", "t": 2026.0, "status": null, "ff": "Vera Rubin Superchip (1 Vera CPU + 2 Rubin GPUs) in liquid-cooled NVL72 rack", "mem": 288.0, "memType": "HBM4", "bw": 19200.0, "tdp": null, "sms": 224.0, "tc": 896.0, "cuda": null, "boost": null, "v": { "fp32": [ 130.0, null, "p" ], "fp64": [ 33.0, null, "p" ], "tf32": [ 2000.0, 4000.0, "p" ], "fp16": [ 4000.0, 8000.0, "p" ], "bf16": [ 4000.0, 8000.0, "p" ], "fp8": [ 17500.0, 35000.0, "p" ], "fp6": [ 17500.0, 35000.0, "p" ], "fp4": [ 35000.0, 50000.0, "p" ], "int8": [ 250.0, 500.0, "p" ] }, "how": { "fp32": "NVIDIA: “NVIDIA Rubin GPU: FP32 130 TFLOPS” [nvidia.com]", "fp64": "NVIDIA: “NVIDIA Rubin GPU: FP64 33 TFLOPS” [nvidia.com]", "tf32": "NVIDIA: “NVIDIA Rubin GPU: TF32³ 2 PFLOPS” [nvidia.com]", "fp16": "NVIDIA: “NVIDIA Rubin GPU: FP16/BF16³ 4 PFLOPS” [nvidia.com]", "bf16": "NVIDIA: “NVIDIA Rubin GPU: FP16/BF16³ 4 PFLOPS” [nvidia.com]", "fp8": "NVIDIA: “NVIDIA Rubin GPU: FP8/FP6 Training³ 17.5 PFLOPS (³Dense specification.)” [nvidia.com]", "fp6": "NVIDIA: “NVIDIA Rubin GPU: FP8/FP6 Training³ 17.5 PFLOPS” [nvidia.com]", "fp4": "NVIDIA: “NVIDIA Rubin GPU: NVFP4 Inference² 50 PFLOPS; NVFP4 Training³ 35 PFLOPS (²Sparse specification. ³Dense specification.)” [nvidia.com]", "int8": "NVIDIA: “Individual GPU Specifications, NVIDIA Rubin GPU: INT8² 250 TOPS (²Dense specification.)” [nvidia.com]" }, "na": { "fp64tc": "NVIDIA doesn't publish this figure", "int4": "NVIDIA doesn't publish this figure" }, "headline": null, "anchor": null, "notes": "Rack totals (Vera Rubin datasheet Oct26; DGX Vera Rubin NVL72 datasheet Sep26): NVFP4 inference 3,600 PFLOPS (sparse), NVFP4 training 2,520, FP8/FP6 training 1,260, FP16/BF16 288, TF32 144 PFLOPS (dense), FP32 9,360 and FP64 2,400 TFLOPS, 20.7 TB HBM4 | 1,400 TB/s, NVLink 216 TB/s. Divided by 72 these match the per-GPU column (FP64 33.3). Conflicts: per-GPU HBM4 bandwidth is 19.2 TB/s on this page (1,400/72 = 19.4) vs 'up to 22 TB/s' in the Jan-2026 and Jul-2026 NVIDIA blogs and the HGX page per-GPU table. Per-GPU NVLink is 3 TB/s here and in the datasheet ('3 terabytes per second (TB/s) of bandwidth per GPU and 216 TB/s') vs 3.6 TB/s in the Jan-2026 blog and on the HGX page. The 50 PFLOPS NVFP4 inference figure is labelled 'Sparse specification' on product pages, but the Jan-2026 blog footnotes it as '* Transformer Engine compute' (hardware adaptive compression), and it is not 2x the 35 PFLOPS dense training figure. INT8 is only 250 TOPS dense. No per-GPU TDP or clocks are published (rack power MaxP 227 kW, MaxQ 187 kW, MaxLPS 156 kW). No die codename (such as VR200) appears in the NVIDIA sources reviewed.", "sources": [ { "t": "nvidia.com — /en-us/data-center/vera-rubin-nvl72/", "u": "https://www.nvidia.com/en-us/data-center/vera-rubin-nvl72/" }, { "t": "dam-cdn.nvd.orangelogic.com — /AssetLink/56p68o47y6f1yucpubl0ump1c0aif422.pdf", "u": "https://dam-cdn.nvd.orangelogic.com/AssetLink/56p68o47y6f1yucpubl0ump1c0aif422.pdf" }, { "t": "nvidia.com — /en-us/data-center/hgx/", "u": "https://www.nvidia.com/en-us/data-center/hgx/" }, { "t": "developer.nvidia.com — /blog/inside-the-nvidia-rubin-platform-six-new-chips-one-ai-supercomputer/", "u": "https://developer.nvidia.com/blog/inside-the-nvidia-rubin-platform-six-new-chips-one-ai-supercomputer/" }, { "t": "developer.nvidia.com — /blog/inside-nvidia-rubin-gpu-architecture-powering-the-era-of-agentic-ai/", "u": "https://developer.nvidia.com/blog/inside-nvidia-rubin-gpu-architecture-powering-the-era-of-agentic-ai/" }, { "t": "dam-cdn.nvd.orangelogic.com — /AssetLink/05p8225000qc1l606krfd80k80kis0om.pdf", "u": "https://dam-cdn.nvd.orangelogic.com/AssetLink/05p8225000qc1l606krfd80k80kis0om.pdf" }, { "t": "nvidianews.nvidia.com — /news/vera-rubin-full-production-agentic-ai-factory", "u": "https://nvidianews.nvidia.com/news/vera-rubin-full-production-agentic-ai-factory" } ], "aka": null }, { "id": "b300", "name": "NVIDIA B300 Blackwell Ultra (HGX, per GPU)", "short": "B300", "seg": "datacenter", "arch": "Blackwell Ultra", "archGroup": "Blackwell Ultra", "cls": "blackwell-ultra", "clsLabel": "Blackwell Ultra (B300, GB300)", "chip": null, "date": "2025-03", "t": 2025.1666666666667, "status": null, "ff": "SXM (HGX B300 8-GPU baseboard; DGX B300)", "mem": 270.0, "memType": "HBM3E", "bw": 7700.0, "tdp": 1100.0, "sms": null, "tc": null, "cuda": null, "boost": null, "v": { "fp32": [ 75.0, null, "p" ], "fp64": [ 1.2, null, "p" ], "fp64tc": [ 1.2, null, "p" ], "tf32": [ 1100.0, 2200.0, "p" ], "fp16": [ 2200.0, 4500.0, "p" ], "bf16": [ 2200.0, 4500.0, "p" ], "fp8": [ 4500.0, 9000.0, "p" ], "fp6": [ 4500.0, 9000.0, "p" ], "fp4": [ 14000.0, 18000.0, "p" ], "int8": [ 150.0, 300.0, "p" ] }, "how": { "fp32": "NVIDIA: “Table 3, Per GPU Specs, HGX B300: FP32 75 teraFLOPS” [dam-cdn.nvd.orangelogic.com]", "fp64": "NVIDIA: “Table 3, Per GPU Specs, HGX B300: FP64 Tensor Core | FP64 1.2 teraFLOPS” [dam-cdn.nvd.orangelogic.com]", "fp64tc": "NVIDIA: “Table 3, Per GPU Specs, HGX B300: FP64 Tensor Core | FP64 1.2 teraFLOPS” [dam-cdn.nvd.orangelogic.com]", "tf32": "NVIDIA: “Table 3, Per GPU Specs, HGX B300: TF32 Tensor Core Dense/Sparse 1.1/2.2 petaFLOPS” [dam-cdn.nvd.orangelogic.com]", "fp16": "NVIDIA: “Table 3, Per GPU Specs, HGX B300: FP16/BF16 Tensor Core Dense/Sparse 2.2/4.5 petaFLOPS” [dam-cdn.nvd.orangelogic.com]", "bf16": "NVIDIA: “Table 3, Per GPU Specs, HGX B300: FP16/BF16 Tensor Core Dense/Sparse 2.2/4.5 petaFLOPS” [dam-cdn.nvd.orangelogic.com]", "fp8": "NVIDIA: “Table 3, Per GPU Specs, HGX B300: FP8/FP6 Tensor Core Dense/Sparse 4.5/9 petaFLOPS” [dam-cdn.nvd.orangelogic.com]", "fp6": "NVIDIA: “Table 3, Per GPU Specs, HGX B300: FP8/FP6 Tensor Core Dense/Sparse 4.5/9 petaFLOPS” [dam-cdn.nvd.orangelogic.com]", "fp4": "NVIDIA: “Table 3, Per GPU Specs, HGX B300: FP4 Tensor Core Dense/Sparse 14/18 petaFLOPS” [dam-cdn.nvd.orangelogic.com]", "int8": "NVIDIA: “Table 3, Per GPU Specs, HGX B300: INT8 Tensor Core Dense/Sparse 0.15/ 0.30 petaOPS” [dam-cdn.nvd.orangelogic.com]" }, "na": { "int4": "NVIDIA doesn't publish this figure" }, "headline": null, "anchor": null, "notes": "Blackwell Ultra cuts FP64 (1.2 TFLOPS vs 37 on B200) and INT8 (0.3 POPS sparse vs 9). Blackwell Ultra datasheet (Oct25) per-GPU HGX B300: FP4 '18 PFLOPS | 14 PFLOPS' (sparse | dense), FP8/FP6 9 PFLOPS, INT8 307 TOPS, FP16/BF16 '4.5 PLFOPS' (sic), TF32 2.2 PFLOPS (sparse; 'Dense is ½ sparse spec shown'), FP32 75, FP64/FP64 Tensor Core 1.2 TFLOPS. nvidia.com/hgx (8 GPUs): FP4 144 | 108 PFLOPS (= 18 | 13.5 per GPU), FP8/FP6 72, INT8 3 POPS (= 375 TOPS sparse per GPU), FP16/BF16 36, TF32 18 PFLOPS, FP32 600, FP64/FP64 Tensor Core 10 TFLOPS (= 1.25 per GPU), Total Memory 2.1 TB. DGX B300 datasheet (Feb26): '2.1 TB total, 62 TB/s HBM3e bandwidth', 'FP4 Tensor Core* - 144 PFLOPS | 108 PFLOPS', 'FP8/FP6 Tensor Core** - 72 PFLOPS', 14.5 kW (busbar). Conflict: per-GPU INT8 sparse is 300 TOPS (brief), 307 TOPS (datasheet) or 375 TOPS (HGX page, 3 POPS / 8). Versus GB300: 1,100 W vs 1,400 W, FP4 18 | 14 vs 20 | 15 PFLOPS, 270 vs 279 GB; NVIDIA publishes no clocks. Brief Table 3: HGX B300 interconnect 'NVLink 5, PCIe Gen6'.", "sources": [ { "t": "dam-cdn.nvd.orangelogic.com — /AssetLink/gl2l4l4812s5fw0p614s6i8bv6mi3vx5.pdf", "u": "https://dam-cdn.nvd.orangelogic.com/AssetLink/gl2l4l4812s5fw0p614s6i8bv6mi3vx5.pdf" }, { "t": "dam-cdn.nvd.orangelogic.com — /AssetLink/1k0p832eq8r5ca0u5383ie5o4tp3bst1.pdf", "u": "https://dam-cdn.nvd.orangelogic.com/AssetLink/1k0p832eq8r5ca0u5383ie5o4tp3bst1.pdf" }, { "t": "nvidia.com — /en-us/data-center/hgx/", "u": "https://www.nvidia.com/en-us/data-center/hgx/" }, { "t": "nvidia.com — /en-us/data-center/dgx-b300/", "u": "https://www.nvidia.com/en-us/data-center/dgx-b300/" }, { "t": "dam-cdn.nvd.orangelogic.com — /AssetLink/625w0j7hnw6f07ui7fo63211mti2v08o.pdf", "u": "https://dam-cdn.nvd.orangelogic.com/AssetLink/625w0j7hnw6f07ui7fo63211mti2v08o.pdf" }, { "t": "developer.nvidia.com — /blog/inside-nvidia-blackwell-ultra-the-chip-powering-the-ai-factory-era/", "u": "https://developer.nvidia.com/blog/inside-nvidia-blackwell-ultra-the-chip-powering-the-ai-factory-era/" } ], "aka": null }, { "id": "dgx-spark-gb10", "name": "NVIDIA DGX Spark (GB10)", "short": "DGX Spark", "seg": "datacenter", "arch": "Blackwell", "archGroup": "Blackwell", "cls": "blackwell-gb10", "clsLabel": "Blackwell GB10 (DGX Spark)", "chip": "GB10", "date": "2025-03", "t": 2025.1666666666667, "status": null, "ff": "desktop system, 150 mm x 150 mm x 50.5 mm; GB10 SoC with integrated Blackwell GPU", "mem": 128.0, "memType": "LPDDR5x, unified CPU+GPU", "bw": 273.0, "tdp": 140.0, "sms": 48.0, "tc": 48.0, "cuda": 6144.0, "boost": 2400.0, "v": { "fp32": [ 29.4912, null, "d" ], "fp4": [ 500.0, 1000.0, "p" ] }, "how": { "fp32": "Derived: 2 × 6,144 CUDA cores × 2,400 MHz boost clock", "fp4": "NVIDIA: “Tensor Performance¹ Up to 1 PFLOP FP4 (¹Theoretical FP4 TOPS using the sparsity feature.); GB10 whitepaper Table 2: AI TOPS performance 1 PFLOP NVFP4 Sparse” (dense = half the published sparse figure) [nvidia.com]" }, "na": { "fp64": "NVIDIA doesn't publish this figure", "fp64tc": "NVIDIA doesn't publish this figure", "tf32": "NVIDIA doesn't publish this figure", "fp16": "NVIDIA doesn't publish this figure", "bf16": "NVIDIA doesn't publish this figure", "fp8": "NVIDIA doesn't publish this figure", "fp6": "NVIDIA doesn't publish this figure", "int8": "NVIDIA doesn't publish this figure", "int4": "NVIDIA doesn't publish this figure" }, "headline": null, "anchor": null, "notes": "NVIDIA publishes no other precision for GB10/DGX Spark; the whitepaper lists supported precisions without rates ('CUDA: FP16, FP32; Tensor: FP4, FP8, FP16, BF16'). The whitepaper's 'Tensor cores 48 (1 per SM)' differs from the 4-per-SM layout of other Blackwell GPUs; recorded as printed. Whitepaper Table 1: Power 140 Watts ('SoC only, typical'), 128 GB LPDDR5x at 8,533 Mbps. DGX Spark datasheet (Sep26): 'Tensor Performance¹ 1 PFLOP', 'Memory Bandwidth Up to 273 GB/s'. The 140 W TDP covers CPU and GPU.", "sources": [ { "t": "nvidia.com — /en-us/products/workstations/dgx-spark/", "u": "https://www.nvidia.com/en-us/products/workstations/dgx-spark/" }, { "t": "dam-cdn.nvd.orangelogic.com — /AssetLink/es6d60li4v5hybk461p65is6os33c48h.pdf", "u": "https://dam-cdn.nvd.orangelogic.com/AssetLink/es6d60li4v5hybk461p65is6os33c48h.pdf" }, { "t": "nvidia.com — /content/dam/en-zz/Solutions/dgx-spark/nvidia-gb10-superchip-whitepaper.pdf", "u": "https://www.nvidia.com/content/dam/en-zz/Solutions/dgx-spark/nvidia-gb10-superchip-whitepaper.pdf" } ], "aka": null }, { "id": "gb300", "name": "NVIDIA GB300 Blackwell Ultra (NVL72, per GPU)", "short": "GB300", "seg": "datacenter", "arch": "Blackwell Ultra", "archGroup": "Blackwell Ultra", "cls": "blackwell-ultra", "clsLabel": "Blackwell Ultra (B300, GB300)", "chip": null, "date": "2025-03", "t": 2025.1666666666667, "status": null, "ff": "Grace Blackwell Ultra Superchip (1 Grace CPU + 2 Blackwell Ultra GPUs) in liquid-cooled NVL72 rack", "mem": 279.0, "memType": "HBM3E", "bw": 8000.0, "tdp": 1400.0, "sms": null, "tc": null, "cuda": null, "boost": null, "v": { "fp32": [ 80.0, null, "p" ], "fp64": [ 1.3, null, "p" ], "fp64tc": [ 1.3, null, "p" ], "tf32": [ 1250.0, 2500.0, "p" ], "fp16": [ 2500.0, 5000.0, "p" ], "bf16": [ 2500.0, 5000.0, "p" ], "fp8": [ 5000.0, 10000.0, "p" ], "fp6": [ 5000.0, 10000.0, "p" ], "fp4": [ 15000.0, 20000.0, "p" ], "int8": [ 165.0, 330.0, "p" ] }, "how": { "fp32": "NVIDIA: “Individual Blackwell Ultra GPU Specifications, GB300 NVL72: FP32 80 TFLOPS” [dam-cdn.nvd.orangelogic.com]", "fp64": "NVIDIA: “Individual Blackwell Ultra GPU Specifications, GB300 NVL72: FP64/FP64 Tensor Core 1.3 TFLOPS” [dam-cdn.nvd.orangelogic.com]", "fp64tc": "NVIDIA: “Individual Blackwell Ultra GPU Specifications, GB300 NVL72: FP64/FP64 Tensor Core 1.3 TFLOPS” [dam-cdn.nvd.orangelogic.com]", "tf32": "NVIDIA: “Individual Blackwell Ultra GPU Specifications, GB300 NVL72: TF32 Tensor Core² 2.5 PFLOPS” [dam-cdn.nvd.orangelogic.com]", "fp16": "NVIDIA: “Individual Blackwell Ultra GPU Specifications, GB300 NVL72: FP16/BF16 Tensor Core² 5 PFLOPS” [dam-cdn.nvd.orangelogic.com]", "bf16": "NVIDIA: “Individual Blackwell Ultra GPU Specifications, GB300 NVL72: FP16/BF16 Tensor Core² 5 PFLOPS” [dam-cdn.nvd.orangelogic.com]", "fp8": "NVIDIA: “Individual Blackwell Ultra GPU Specifications, GB300 NVL72: FP8/FP6 Tensor Core² 10 PFLOPS (²Specification in sparse. Dense is ½ sparse spec shown.)” [dam-cdn.nvd.orangelogic.com]", "fp6": "NVIDIA: “Individual Blackwell Ultra GPU Specifications, GB300 NVL72: FP8/FP6 Tensor Core² 10 PFLOPS” [dam-cdn.nvd.orangelogic.com]", "fp4": "NVIDIA: “Individual Blackwell Ultra GPU Specifications, GB300 NVL72: FP4 Tensor Core¹ 20 PFLOPS | 15 PFLOPS (¹Specification in Sparse | Dense)” [dam-cdn.nvd.orangelogic.com]", "int8": "NVIDIA: “INT8 Tensor Core² 330 TOPS (² Specification in sparse. Dense is ½ sparse spec shown.)” [dam-cdn.nvd.orangelogic.com]" }, "na": { "int4": "NVIDIA doesn't publish this figure" }, "headline": null, "anchor": null, "notes": "nvidia.com/gb300-nvl72 (72 GPUs): FP4 '1440 | 1080' PFLOPS (1080 marked 'Without sparsity'), FP8/FP6 720 PFLOPS, INT8 24 POPS, FP16/BF16 360, TF32 180 PFLOPS ('All Tensor Core specifications are with sparsity unless otherwise noted'), FP32 6 PFLOPS, FP64/FP64 Tensor Core 100 TFLOPS, '20 TB | Up to 576 TB/s'. Rack totals divided by 72 give FP64 1.39 TFLOPS and INT8 333 TOPS sparse vs the datasheet's per-GPU 1.3 TFLOPS and 330 TOPS; the page's FP32 6 PFLOPS / 72 = 83 TFLOPS vs 80 per GPU (brief Table 2: 5,760 teraFLOPS). Blackwell Ultra blog Table 2: 'Max power (TGP) Up to 1,400W', 'Max HBM capacity 288 GB HBM3E' (GB300 SKU: 279 GB). Technical brief Figure 4: '15PF Dense FP4 | 279GB HBM3e'. DGX GB300 datasheet: 'FP4 Tensor Core: 1,440 PFLOPS | 1,080 PFLOPS*', 'FP8/FP6 Tensor Core: 720 PFLOPS', '1.4 exaFLOPS for inference and 360 PFLOPS for training'. Versus HGX B300: 1,400 W vs 1,100 W, FP4 20 | 15 vs 18 | 14 PFLOPS, FP64 1.3 vs 1.2 TFLOPS; NVIDIA publishes no clocks.", "sources": [ { "t": "dam-cdn.nvd.orangelogic.com — /AssetLink/1k0p832eq8r5ca0u5383ie5o4tp3bst1.pdf", "u": "https://dam-cdn.nvd.orangelogic.com/AssetLink/1k0p832eq8r5ca0u5383ie5o4tp3bst1.pdf" }, { "t": "dam-cdn.nvd.orangelogic.com — /AssetLink/gl2l4l4812s5fw0p614s6i8bv6mi3vx5.pdf", "u": "https://dam-cdn.nvd.orangelogic.com/AssetLink/gl2l4l4812s5fw0p614s6i8bv6mi3vx5.pdf" }, { "t": "developer.nvidia.com — /blog/inside-nvidia-blackwell-ultra-the-chip-powering-the-ai-factory-era/", "u": "https://developer.nvidia.com/blog/inside-nvidia-blackwell-ultra-the-chip-powering-the-ai-factory-era/" }, { "t": "nvidia.com — /en-us/data-center/gb300-nvl72/", "u": "https://www.nvidia.com/en-us/data-center/gb300-nvl72/" }, { "t": "dam-cdn.nvd.orangelogic.com — /AssetLink/1h2h8if7map561705sb3rk02xeg430v3.pdf", "u": "https://dam-cdn.nvd.orangelogic.com/AssetLink/1h2h8if7map561705sb3rk02xeg430v3.pdf" } ], "aka": null }, { "id": "rtx-pro-6000-blackwell-server", "name": "NVIDIA RTX PRO 6000 Blackwell Server Edition", "short": "RTX PRO 6000 Server", "seg": "datacenter", "arch": "Blackwell", "archGroup": "Blackwell", "cls": "blackwell-pro", "clsLabel": "Blackwell GB20x (RTX PRO)", "chip": "GB202", "date": "2025-03", "t": 2025.1666666666667, "status": null, "ff": "PCIe Gen5 x16, FHFL 10.5 in, dual-slot, passive (air); liquid-cooled single-slot FHXL variant", "mem": 96.0, "memType": "GDDR7 (ECC)", "bw": 1597.0, "tdp": 600.0, "sms": null, "tc": 752.0, "cuda": 24064.0, "boost": 2430.0, "v": { "fp32": [ 120.0, null, "p" ], "fp64": [ 1.875, null, "d" ], "tf32": [ 234.0, 468.0, "p" ], "fp16": [ 468.0, 936.0, "d" ], "bf16": [ 468.0, 936.0, "d" ], "fp8": [ 936.0, 1872.0, "d" ], "fp4": [ 1872.0, 3744.0, "d" ], "int8": [ 936.0, 1872.0, "d" ] }, "how": { "fp32": "NVIDIA: “Single-Precision Performance (FP32) 120 TFLOPS” [nvidia.com]", "fp64": "Derived: FP32 ÷ 64 (this architecture's FP64 rate)", "tf32": "NVIDIA: “TF32 Tensor Core 234 TFLOPS” [nvidia.com]", "fp16": "Derived from NVIDIA's published TF32 figure of 234 dense. On RTX PRO Blackwell, FP16 runs at twice the TF32 rate", "bf16": "Derived from NVIDIA's published TF32 figure of 234 dense. On RTX PRO Blackwell, BF16 runs at twice the TF32 rate", "fp8": "Derived from NVIDIA's published TF32 figure of 234 dense. On RTX PRO Blackwell, FP8 runs at 4× the TF32 rate", "fp4": "Derived from NVIDIA's published TF32 figure of 234 dense. On RTX PRO Blackwell, FP4 runs at 8× the TF32 rate", "int8": "Derived from NVIDIA's published TF32 figure of 234 dense. On RTX PRO Blackwell, INT8 runs at 4× the TF32 rate" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "fp6": "RTX Blackwell supports FP6, but NVIDIA publishes no FP6 rate for it", "int4": "NVIDIA lists no INT4 rate for Blackwell" }, "headline": null, "anchor": "Derived from NVIDIA's published TF32 figure of 234 dense. ", "notes": "NVIDIA's Server Edition page lists FP4 4 PFLOPS, FP8 2 PFLOPS, FP16/BF16 1 PFLOP and TF32 234 TFLOPS with no dense/sparse labels. TF32 234 TFLOPS is the dense rate of 188 SMs at the 2,430 MHz boost; the others match the sparse rates rounded to one digit (936, 1,872 and 3,743 TFLOPS), so this page derives every tensor figure from the exact TF32 number.", "sources": [ { "t": "nvidia.com — /en-us/data-center/rtx-pro-6000-blackwell-server-edition/", "u": "https://www.nvidia.com/en-us/data-center/rtx-pro-6000-blackwell-server-edition/" }, { "t": "dam-cdn.nvd.orangelogic.com — /AssetLink/707m1632ypg4du1fj3ci1jo3h4w1k78j.pdf", "u": "https://dam-cdn.nvd.orangelogic.com/AssetLink/707m1632ypg4du1fj3ci1jo3h4w1k78j.pdf" }, { "t": "dam-cdn.nvd.orangelogic.com — /AssetLink/3km2720jiy76r06ctf8mxg21743p1058.pdf", "u": "https://dam-cdn.nvd.orangelogic.com/AssetLink/3km2720jiy76r06ctf8mxg21743p1058.pdf" }, { "t": "nvidia.com — /content/dam/en-zz/Solutions/design-visualization/quadro-product-literature/NVID", "u": "https://www.nvidia.com/content/dam/en-zz/Solutions/design-visualization/quadro-product-literature/NVIDIA-RTX-Blackwell-PRO-GPU-Architecture-v1.0.pdf" } ], "aka": null }, { "id": "h200-nvl", "name": "NVIDIA H200 NVL", "short": "H200 NVL", "seg": "datacenter", "arch": "Hopper", "archGroup": "Hopper", "cls": "hopper", "clsLabel": "Hopper (H100, H200)", "chip": "GH100", "date": "2024-11", "t": 2024.8333333333333, "status": null, "ff": "PCIe Gen5 x16 card, FHFL 10.5 in, dual-slot, passive; 2- or 4-way NVLink bridge", "mem": 141.0, "memType": "HBM3e", "bw": 4813.0, "tdp": 600.0, "sms": null, "tc": null, "cuda": null, "boost": 1785.0, "v": { "fp32": [ 60.0, null, "p" ], "fp64": [ 30.0, null, "p" ], "fp64tc": [ 60.0, null, "p" ], "tf32": [ 417.5, 835.0, "p" ], "fp16": [ 835.5, 1671.0, "p" ], "bf16": [ 835.5, 1671.0, "p" ], "fp8": [ 1670.5, 3341.0, "p" ], "int8": [ 1670.5, 3341.0, "p" ] }, "how": { "fp32": "NVIDIA: “FP32 60 TFLOPS” [dam-cdn.nvd.orangelogic.com]", "fp64": "NVIDIA: “FP64 30 TFLOPS” [dam-cdn.nvd.orangelogic.com]", "fp64tc": "NVIDIA: “FP64 Tensor Core 60 TFLOPS” [dam-cdn.nvd.orangelogic.com]", "tf32": "NVIDIA: “TF32 Tensor Core² 835 TFLOPS (²With sparsity.)” (dense = half the published sparse figure) [dam-cdn.nvd.orangelogic.com]", "fp16": "NVIDIA: “FP16 Tensor Core² 1,671 TFLOPS” (dense = half the published sparse figure) [dam-cdn.nvd.orangelogic.com]", "bf16": "NVIDIA: “BFLOAT16 Tensor Core² 1,671 TFLOPS” (dense = half the published sparse figure) [dam-cdn.nvd.orangelogic.com]", "fp8": "NVIDIA: “FP8 Tensor Core² 3,341 TFLOPS” (dense = half the published sparse figure) [dam-cdn.nvd.orangelogic.com]", "int8": "NVIDIA: “INT8 Tensor Core² 3,341 TFLOPS (unit printed as TFLOPS)” (dense = half the published sparse figure) [dam-cdn.nvd.orangelogic.com]" }, "na": { "fp6": "No FP6 tensor cores before Blackwell", "fp4": "No FP4 tensor cores before Blackwell", "int4": "Hopper dropped INT4 tensor support" }, "headline": null, "anchor": null, "notes": "Throughput is identical to H100 NVL (both 1,785 MHz boost) although TDP is 600 W vs 400 W. Datasheet/page TDP 'Up to 600W (configurable)', bandwidth '4.8TB/s'. Same preliminary-spec footnote and INT8 unit error as H200 SXM. Dense figures are not published. The product brief is headed 'NVIDIA CONFIDENTIAL | PREPARED AND PROVIDED UNDER NDA' but is linked publicly from nvidia.com/h200. NVIDIA does not publish the SM count.", "sources": [ { "t": "dam-cdn.nvd.orangelogic.com — /AssetLink/5o2qgy5d2835ve2pm11i62kv8mphqta8.pdf", "u": "https://dam-cdn.nvd.orangelogic.com/AssetLink/5o2qgy5d2835ve2pm11i62kv8mphqta8.pdf" }, { "t": "nvidia.com — /en-us/data-center/h200/", "u": "https://www.nvidia.com/en-us/data-center/h200/" }, { "t": "dam-cdn.nvd.orangelogic.com — /AssetLink/7n7vya4684sdccfyy6kv37ek5lw702h7.pdf", "u": "https://dam-cdn.nvd.orangelogic.com/AssetLink/7n7vya4684sdccfyy6kv37ek5lw702h7.pdf" } ], "aka": null }, { "id": "b100", "name": "NVIDIA B100 (HGX, per GPU)", "short": "B100", "seg": "datacenter", "arch": "Blackwell", "archGroup": "Blackwell", "cls": "blackwell-dc", "clsLabel": "Blackwell (B200, GB200)", "chip": null, "date": "2024-03", "t": 2024.1666666666667, "status": "announced", "ff": "SXM (HGX B100 8-GPU baseboard)", "mem": null, "memType": null, "bw": null, "tdp": null, "sms": null, "tc": null, "cuda": null, "boost": null, "v": { "fp32": [ 60.0, null, "p" ], "fp64": [ 30.0, null, "p" ], "fp64tc": [ 30.0, null, "p" ], "tf32": [ 875.0, 1750.0, "p" ], "fp16": [ 1750.0, 3500.0, "p" ], "bf16": [ 1750.0, 3500.0, "p" ], "fp8": [ 3500.0, 7000.0, "p" ], "fp6": [ 3500.0, 7000.0, "p" ], "fp4": [ 7000.0, 14000.0, "p" ], "int8": [ 3500.0, 7000.0, "p" ] }, "how": { "fp32": "NVIDIA: “HGX B100 (8 GPUs): FP32 480 TFLOPS; 480/8 = 60 TFLOPS per GPU” [arquivo.pt]", "fp64": "NVIDIA: “HGX B100 (8 GPUs): FP64 240 TFLOPS; 240/8 = 30 TFLOPS per GPU” [arquivo.pt]", "fp64tc": "NVIDIA: “HGX B100 (8 GPUs): FP64 Tensor Core 240 TFLOPS; 240/8 = 30 TFLOPS per GPU” [arquivo.pt]", "tf32": "NVIDIA: “HGX B100 (8 GPUs): TF32 Tensor Core* 14 PFLOPS; 14/8 = 1.75 PFLOPS per GPU” (dense = half the published sparse figure) [arquivo.pt]", "fp16": "NVIDIA: “HGX B100 (8 GPUs): FP16/BF16 Tensor Core* 28 PFLOPS; 28/8 = 3.5 PFLOPS per GPU” (dense = half the published sparse figure) [arquivo.pt]", "bf16": "NVIDIA: “HGX B100 (8 GPUs): FP16/BF16 Tensor Core* 28 PFLOPS; 28/8 = 3.5 PFLOPS per GPU” (dense = half the published sparse figure) [arquivo.pt]", "fp8": "NVIDIA: “HGX B100 (8 GPUs): FP8/FP6 Tensor Core* 56 PFLOPS; 56/8 = 7 PFLOPS per GPU” (dense = half the published sparse figure) [arquivo.pt]", "fp6": "NVIDIA: “HGX B100 (8 GPUs): FP8/FP6 Tensor Core* 56 PFLOPS; 56/8 = 7 PFLOPS per GPU” (dense = half the published sparse figure) [arquivo.pt]", "fp4": "NVIDIA: “HGX B100 (8 GPUs): FP4 Tensor Core* 112 PFLOPS (* With sparsity); 112/8 = 14 PFLOPS per GPU” (dense = half the published sparse figure) [arquivo.pt]", "int8": "NVIDIA: “HGX B100 (8 GPUs): INT8 Tensor Core* 56 POPS; 56/8 = 7 POPS per GPU” (dense = half the published sparse figure) [arquivo.pt]" }, "na": { "int4": "NVIDIA doesn't publish this figure" }, "headline": null, "anchor": null, "notes": "Only NVIDIA source found: the nvidia.com/hgx page as archived by arquivo.pt on 2024-10-10. The 2024-05-11 capture shows the same numbers in one row: 'HPC and AI compute (FP64/TF32/FP16/FP8/FP4)* 240TF/14PF/28PF/56PF/112PF'. web.archive.org returned HTTP 429 during this run. The current nvidia.com/hgx page, the Oct-2025 Blackwell datasheet and the Blackwell technical brief V2.1 no longer mention B100, and no NVIDIA statement that HGX B100 shipped was found, hence status 'announced'. Per-GPU HBM capacity, bandwidth and TDP were not on that page (memory only as 'Up to 1.5TB' per 8-GPU board). The original March-2024 Blackwell technical brief/datasheet PDFs (nvdam.widen.net) now return 404 and were not archived.", "sources": [ { "t": "arquivo.pt — /wayback/20241010140532/https://www.nvidia.com/en-us/data-center/hgx/", "u": "https://arquivo.pt/wayback/20241010140532/https://www.nvidia.com/en-us/data-center/hgx/" }, { "t": "arquivo.pt — /wayback/20240511195711/https://www.nvidia.com/en-us/data-center/hgx/", "u": "https://arquivo.pt/wayback/20240511195711/https://www.nvidia.com/en-us/data-center/hgx/" } ], "aka": null }, { "id": "b200", "name": "NVIDIA B200 (HGX, per GPU)", "short": "B200", "seg": "datacenter", "arch": "Blackwell", "archGroup": "Blackwell", "cls": "blackwell-dc", "clsLabel": "Blackwell (B200, GB200)", "chip": null, "date": "2024-03", "t": 2024.1666666666667, "status": null, "ff": "SXM (HGX B200 8-GPU baseboard; DGX B200)", "mem": 180.0, "memType": "HBM3E", "bw": 7700.0, "tdp": 1000.0, "sms": null, "tc": null, "cuda": null, "boost": null, "v": { "fp32": [ 75.0, null, "p" ], "fp64": [ 37.0, null, "p" ], "fp64tc": [ 37.0, null, "p" ], "tf32": [ 1100.0, 2200.0, "p" ], "fp16": [ 2200.0, 4500.0, "p" ], "bf16": [ 2200.0, 4500.0, "p" ], "fp8": [ 4500.0, 9000.0, "p" ], "fp6": [ 4500.0, 9000.0, "p" ], "fp4": [ 9000.0, 18000.0, "p" ], "int8": [ 4500.0, 9000.0, "p" ] }, "how": { "fp32": "NVIDIA: “Table 3, Per GPU Specs, HGX B200: FP32 75 teraFLOPS” [dam-cdn.nvd.orangelogic.com]", "fp64": "NVIDIA: “Table 3, Per GPU Specs, HGX B200: FP64 Tensor Core | FP64 37 teraFLOPS” [dam-cdn.nvd.orangelogic.com]", "fp64tc": "NVIDIA: “Table 3, Per GPU Specs, HGX B200: FP64 Tensor Core | FP64 37 teraFLOPS” [dam-cdn.nvd.orangelogic.com]", "tf32": "NVIDIA: “Table 3, Per GPU Specs, HGX B200: TF32 Tensor Core Dense/Sparse 1.1/2.2 petaFLOPS” [dam-cdn.nvd.orangelogic.com]", "fp16": "NVIDIA: “Table 3, Per GPU Specs, HGX B200: FP16/BF16 Tensor Core Dense/Sparse 2.2/4.5 petaFLOPS” [dam-cdn.nvd.orangelogic.com]", "bf16": "NVIDIA: “Table 3, Per GPU Specs, HGX B200: FP16/BF16 Tensor Core Dense/Sparse 2.2/4.5 petaFLOPS” [dam-cdn.nvd.orangelogic.com]", "fp8": "NVIDIA: “Table 3, Per GPU Specs, HGX B200: FP8/FP6 Tensor Core Dense/Sparse 4.5/9 petaFLOPS” [dam-cdn.nvd.orangelogic.com]", "fp6": "NVIDIA: “Table 3, Per GPU Specs, HGX B200: FP8/FP6 Tensor Core Dense/Sparse 4.5/9 petaFLOPS” [dam-cdn.nvd.orangelogic.com]", "fp4": "NVIDIA: “Table 3, Per GPU Specs, HGX B200: FP4 Tensor Core Dense/Sparse 9/18 petaFLOPS” [dam-cdn.nvd.orangelogic.com]", "int8": "NVIDIA: “Table 3, Per GPU Specs, HGX B200: INT8 Tensor Core Dense/Sparse 4.5/9 petaOPS” [dam-cdn.nvd.orangelogic.com]" }, "na": { "int4": "NVIDIA doesn't publish this figure" }, "headline": null, "anchor": null, "notes": "Blackwell datasheet (Oct25) per-GPU HGX B200 column, sparse with 'Dense is one-half of the sparse spec shown': FP4 18, FP8/FP6 9 PFLOPS, INT8 9 POPS, FP16/BF16 4.5, TF32 2.2 PFLOPS, FP32 75, FP64/FP64 Tensor Core 37 TFLOPS. nvidia.com/hgx (8 GPUs): FP4 144 | 72 PFLOPS (sparse | dense), FP8/FP6 72, INT8 72 POPS, FP16/BF16 36, TF32 18 PFLOPS (sparse), FP32 600, FP64/FP64 Tensor Core 296 TFLOPS, Total Memory 1.4 TB. DGX B200 datasheet (Oct25): 'FP4 Tensor Core: 144 | 72* petaFLOPS', 'FP8 Tensor Core: 72 | 36* petaFLOPS' (*sparse | dense), '1,440 GB total, 64 TB/s HBM3e bandwidth', ~14.3 kW max. Conflicts: memory 180 GB (datasheet; DGX 1,440/8) vs 'Up to 192 GB HBM3e | 7.7 TB/s' (technical brief V2.1 Table 3); bandwidth 7.7 TB/s (datasheet, brief) vs 8 TB/s implied by DGX B200's 64 TB/s. NVIDIA's 2024 HGX page (arquivo.pt 2024-10-10) listed HGX B200 FP32 640 and FP64/FP64 Tensor Core 320 TFLOPS (80 and 40 per GPU) and memory 'Up to 1.5TB', so FP32/FP64 were later revised to 75/37. HGX B200 vs GB200: up to 1,000 W vs 1,200 W per GPU and ~10% lower published throughput (FP4 18 vs 20 PFLOPS sparse); NVIDIA publishes no clocks or SM counts. FP16/BF16 dense '2.2' is 4.5/2 rounded down. The datasheet and brief list PCIe Gen5 for HGX B200, while NVIDIA's Blackwell Ultra and Rubin blogs list the Blackwell GPU's PCIe as Gen 6 (256 GB/s).", "sources": [ { "t": "dam-cdn.nvd.orangelogic.com — /AssetLink/gl2l4l4812s5fw0p614s6i8bv6mi3vx5.pdf", "u": "https://dam-cdn.nvd.orangelogic.com/AssetLink/gl2l4l4812s5fw0p614s6i8bv6mi3vx5.pdf" }, { "t": "dam-cdn.nvd.orangelogic.com — /AssetLink/y441155802qub41q118b2852i557jem5.pdf", "u": "https://dam-cdn.nvd.orangelogic.com/AssetLink/y441155802qub41q118b2852i557jem5.pdf" }, { "t": "nvidia.com — /en-us/data-center/hgx/", "u": "https://www.nvidia.com/en-us/data-center/hgx/" }, { "t": "nvidia.com — /en-us/data-center/dgx-b200/", "u": "https://www.nvidia.com/en-us/data-center/dgx-b200/" }, { "t": "dam-cdn.nvd.orangelogic.com — /AssetLink/h226p7256j0xwmhmx4qqc1t3dv4jqg2m.pdf", "u": "https://dam-cdn.nvd.orangelogic.com/AssetLink/h226p7256j0xwmhmx4qqc1t3dv4jqg2m.pdf" }, { "t": "arquivo.pt — /wayback/20241010140532/https://www.nvidia.com/en-us/data-center/hgx/", "u": "https://arquivo.pt/wayback/20241010140532/https://www.nvidia.com/en-us/data-center/hgx/" } ], "aka": null }, { "id": "gb200", "name": "NVIDIA GB200 (NVL72, per GPU)", "short": "GB200", "seg": "datacenter", "arch": "Blackwell", "archGroup": "Blackwell", "cls": "blackwell-dc", "clsLabel": "Blackwell (B200, GB200)", "chip": null, "date": "2024-03", "t": 2024.1666666666667, "status": null, "ff": "GB200 Grace Blackwell Superchip (1 Grace CPU + 2 Blackwell GPUs) in liquid-cooled NVL72 rack (also GB200 NVL4)", "mem": 186.0, "memType": "HBM3E", "bw": 8000.0, "tdp": 1200.0, "sms": null, "tc": null, "cuda": null, "boost": null, "v": { "fp32": [ 80.0, null, "p" ], "fp64": [ 40.0, null, "p" ], "fp64tc": [ 40.0, null, "p" ], "tf32": [ 1250.0, 2500.0, "p" ], "fp16": [ 2500.0, 5000.0, "p" ], "bf16": [ 2500.0, 5000.0, "p" ], "fp8": [ 5000.0, 10000.0, "p" ], "fp6": [ 5000.0, 10000.0, "p" ], "fp4": [ 10000.0, 20000.0, "p" ], "int8": [ 5000.0, 10000.0, "p" ] }, "how": { "fp32": "NVIDIA: “Individual Blackwell GPU Specifications, GB200 NVL72: FP32 80 TFLOPS” [dam-cdn.nvd.orangelogic.com]", "fp64": "NVIDIA: “Individual Blackwell GPU Specifications, GB200 NVL72: FP64/FP64 Tensor Core 40 TFLOPS” [dam-cdn.nvd.orangelogic.com]", "fp64tc": "NVIDIA: “Individual Blackwell GPU Specifications, GB200 NVL72: FP64/FP64 Tensor Core 40 TFLOPS” [dam-cdn.nvd.orangelogic.com]", "tf32": "NVIDIA: “Individual Blackwell GPU Specifications, GB200 NVL72: TF32 Tensor Core² 2.5 PFLOPS” [dam-cdn.nvd.orangelogic.com]", "fp16": "NVIDIA: “Individual Blackwell GPU Specifications, GB200 NVL72: FP16/BF16 Tensor Core² 5 PFLOPS” [dam-cdn.nvd.orangelogic.com]", "bf16": "NVIDIA: “Individual Blackwell GPU Specifications, GB200 NVL72: FP16/BF16 Tensor Core² 5 PFLOPS” [dam-cdn.nvd.orangelogic.com]", "fp8": "NVIDIA: “Individual Blackwell GPU Specifications, GB200 NVL72: FP8/FP6 Tensor Core² 10 PFLOPS” [dam-cdn.nvd.orangelogic.com]", "fp6": "NVIDIA: “Individual Blackwell GPU Specifications, GB200 NVL72: FP8/FP6 Tensor Core² 10 PFLOPS” [dam-cdn.nvd.orangelogic.com]", "fp4": "NVIDIA: “Individual Blackwell GPU Specifications, GB200 NVL72: FP4 Tensor Core² 20 PFLOPS (²Specifications in sparse. Dense is one-half of the sparse spec shown.)” [dam-cdn.nvd.orangelogic.com]", "int8": "NVIDIA: “Individual Blackwell GPU Specifications, GB200 NVL72: INT8 Tensor Core² 10 POPS” [dam-cdn.nvd.orangelogic.com]" }, "na": { "int4": "NVIDIA doesn't publish this figure" }, "headline": null, "anchor": null, "notes": "nvidia.com/gb200-nvl72, per superchip (2 GPUs): NVFP4 40 | 20 PFLOPS (sparse | dense), FP8/FP6 20 PFLOPS, INT8 20 POPS, FP16/BF16 10, TF32 5 PFLOPS (sparse), FP32 160, FP64/FP64 Tensor Core 80 TFLOPS, 372 GB HBM3E | 16 TB/s; rack 13.4 TB HBM3E | 576 TB/s (technical brief Table 2 says 13.5 TB). DGX GB200 datasheet: 'FP8/FP6 Tensor Core - 720 PFLOPS | 360 PFLOPS*' (*sparse | dense). Revision conflict: the June-2024 GB200 NVL72 page (arquivo.pt 2024-06-12, '1. Preliminary specifications') listed per superchip FP32 180 TFLOPS and FP64/FP64 Tensor Core 90 TFLOPS (90 and 45 per GPU) and 'Up to 384 GB HBM3e | 16 TB/s' (192 GB per GPU); current documents give 80/40 TFLOPS and 186 GB. Versus HGX B200: up to 1,200 W vs 1,000 W per GPU and higher throughput (FP4 20 vs 18 PFLOPS sparse, FP64 40 vs 37); NVIDIA publishes no clocks. GB200 NVL4 (datasheet column) has the same per-GPU figures and 1,200 W.", "sources": [ { "t": "dam-cdn.nvd.orangelogic.com — /AssetLink/y441155802qub41q118b2852i557jem5.pdf", "u": "https://dam-cdn.nvd.orangelogic.com/AssetLink/y441155802qub41q118b2852i557jem5.pdf" }, { "t": "dam-cdn.nvd.orangelogic.com — /AssetLink/gl2l4l4812s5fw0p614s6i8bv6mi3vx5.pdf", "u": "https://dam-cdn.nvd.orangelogic.com/AssetLink/gl2l4l4812s5fw0p614s6i8bv6mi3vx5.pdf" }, { "t": "nvidia.com — /en-us/data-center/gb200-nvl72/", "u": "https://www.nvidia.com/en-us/data-center/gb200-nvl72/" }, { "t": "dam-cdn.nvd.orangelogic.com — /AssetLink/17q6103pr5b44u60nr7e1jagin3ac2il.pdf", "u": "https://dam-cdn.nvd.orangelogic.com/AssetLink/17q6103pr5b44u60nr7e1jagin3ac2il.pdf" }, { "t": "arquivo.pt — /wayback/20240612040300/https://www.nvidia.com/en-us/data-center/gb200-nvl72/", "u": "https://arquivo.pt/wayback/20240612040300/https://www.nvidia.com/en-us/data-center/gb200-nvl72/" } ], "aka": null }, { "id": "h200-sxm", "name": "NVIDIA H200 SXM", "short": "H200 SXM", "seg": "datacenter", "arch": "Hopper", "archGroup": "Hopper", "cls": "hopper", "clsLabel": "Hopper (H100, H200)", "chip": "GH100", "date": "2023-11", "t": 2023.8333333333333, "status": null, "ff": "SXM module (HGX H200 4-/8-GPU boards)", "mem": 141.0, "memType": "HBM3e", "bw": 4800.0, "tdp": 700.0, "sms": null, "tc": null, "cuda": null, "boost": null, "v": { "fp32": [ 67.0, null, "p" ], "fp64": [ 34.0, null, "p" ], "fp64tc": [ 67.0, null, "p" ], "tf32": [ 494.5, 989.0, "p" ], "fp16": [ 989.5, 1979.0, "p" ], "bf16": [ 989.5, 1979.0, "p" ], "fp8": [ 1979.0, 3958.0, "p" ], "int8": [ 1979.0, 3958.0, "p" ] }, "how": { "fp32": "NVIDIA: “FP32 67 TFLOPS” [dam-cdn.nvd.orangelogic.com]", "fp64": "NVIDIA: “FP64 34 TFLOPS” [dam-cdn.nvd.orangelogic.com]", "fp64tc": "NVIDIA: “FP64 Tensor Core 67 TFLOPS” [dam-cdn.nvd.orangelogic.com]", "tf32": "NVIDIA: “TF32 Tensor Core² 989 TFLOPS (²With sparsity.)” (dense = half the published sparse figure) [dam-cdn.nvd.orangelogic.com]", "fp16": "NVIDIA: “FP16 Tensor Core² 1,979 TFLOPS” (dense = half the published sparse figure) [dam-cdn.nvd.orangelogic.com]", "bf16": "NVIDIA: “BFLOAT16 Tensor Core² 1,979 TFLOPS” (dense = half the published sparse figure) [dam-cdn.nvd.orangelogic.com]", "fp8": "NVIDIA: “FP8 Tensor Core² 3,958 TFLOPS” (dense = half the published sparse figure) [dam-cdn.nvd.orangelogic.com]", "int8": "NVIDIA: “INT8 Tensor Core² 3,958 TFLOPS (unit printed as TFLOPS)” (dense = half the published sparse figure) [dam-cdn.nvd.orangelogic.com]" }, "na": { "fp6": "No FP6 tensor cores before Blackwell", "fp4": "No FP4 tensor cores before Blackwell", "int4": "Hopper dropped INT4 tensor support" }, "headline": null, "anchor": null, "notes": "Datasheet (Nov24) and nvidia.com/h200 carry identical tables, with the H200 columns footnoted '¹Preliminary specifications. May be subject to change.' INT8 is printed in TFLOPS on both (unit error). Dense figures are not published. HGX H200 8-GPU datasheet (Jul24) totals, sparse*: FP8 32 PFLOPS, INT8 32 POPS, FP16/BF16 16 PFLOPS, TF32 8 PFLOPS; FP32 540, FP64 270, FP64 Tensor Core 540 TFLOPS; 1.1TB HBM3e; aggregate bandwidth printed '38GB/s' (typo for TB/s). NVIDIA does not publish H200 SM count or clocks.", "sources": [ { "t": "dam-cdn.nvd.orangelogic.com — /AssetLink/5o2qgy5d2835ve2pm11i62kv8mphqta8.pdf", "u": "https://dam-cdn.nvd.orangelogic.com/AssetLink/5o2qgy5d2835ve2pm11i62kv8mphqta8.pdf" }, { "t": "nvidia.com — /en-us/data-center/h200/", "u": "https://www.nvidia.com/en-us/data-center/h200/" }, { "t": "dam-cdn.nvd.orangelogic.com — /AssetLink/44wa8u63l12ps4ie2870214xa2exoyra.pdf", "u": "https://dam-cdn.nvd.orangelogic.com/AssetLink/44wa8u63l12ps4ie2870214xa2exoyra.pdf" } ], "aka": null }, { "id": "l40s", "name": "NVIDIA L40S", "short": "L40S", "seg": "datacenter", "arch": "Ada", "archGroup": "Ada", "cls": "ada-pro", "clsLabel": "Ada (RTX Ada, L4, L40S)", "chip": "AD102", "date": "2023-08", "t": 2023.5833333333333, "status": null, "ff": "PCIe Gen4 x16, 4.4 in x 10.5 in, dual-slot, passive", "mem": 48.0, "memType": "GDDR6 (ECC)", "bw": 864.0, "tdp": 350.0, "sms": null, "tc": 568.0, "cuda": 18176.0, "boost": 2520.0, "v": { "fp32": [ 91.6, null, "p" ], "fp64": [ 1.4312, null, "d" ], "tf32": [ 183.0, 366.0, "p" ], "fp16": [ 362.05, 733.0, "p" ], "bf16": [ 362.05, 733.0, "p" ], "fp8": [ 733.0, 1466.0, "p" ], "int8": [ 733.0, 1466.0, "p" ], "int4": [ 733.0, 1466.0, "p" ] }, "how": { "fp32": "NVIDIA: “FP32 TFLOPS 91.6” [nvidia.com]", "fp64": "Derived: FP32 ÷ 64 (this architecture's FP64 rate)", "tf32": "NVIDIA: “TF32 Tensor Core TFLOPS 183 I 366* (*With Sparsity)” [nvidia.com]", "fp16": "NVIDIA: “FP16 Tensor Core 362.05 I 733*” [nvidia.com]", "bf16": "NVIDIA: “BFLOAT16 Tensor Core TFLOPS 362.05 I 733*” [nvidia.com]", "fp8": "NVIDIA: “FP8 Tensor Core 733 I 1,466*” [nvidia.com]", "int8": "NVIDIA: “Peak INT8 Tensor TOPS 733 I 1,466*” [nvidia.com]", "int4": "NVIDIA: “Peak INT4 Tensor TOPS 733 | 1,466* (equal to INT8; probably a datasheet error)” [nvidia.com]" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "fp6": "No FP6 tensor cores before Blackwell", "fp4": "No FP4 tensor cores before Blackwell" }, "headline": null, "anchor": "Derived from NVIDIA's published FP16 figure of 362.05 dense. ", "notes": "NVIDIA's L40S datasheet lists INT4 equal to INT8 (733 | 1,466 TOPS). The L40, the same chip, lists INT4 at twice INT8 (724 | 1,448), so the L40S INT4 figure is probably a datasheet error. It is shown as published.", "sources": [ { "t": "nvidia.com — /en-us/data-center/l40s/", "u": "https://www.nvidia.com/en-us/data-center/l40s/" }, { "t": "techpowerup.com — /gpu-specs/l40s.c4173", "u": "https://www.techpowerup.com/gpu-specs/l40s.c4173" } ], "aka": null }, { "id": "gh200", "name": "NVIDIA GH200 (Hopper GPU)", "short": "GH200", "seg": "datacenter", "arch": "Hopper", "archGroup": "Hopper", "cls": "hopper", "clsLabel": "Hopper (H100, H200)", "chip": "GH100 GPU + Grace CPU", "date": "2023-05", "t": 2023.3333333333333, "status": null, "ff": "Superchip module: 1 Grace CPU + 1 Hopper GPU over NVLink-C2C (also GH200 NVL2 = 2 superchips)", "mem": 144.0, "memType": "HBM3e", "bw": 4900.0, "tdp": 1000.0, "sms": null, "tc": null, "cuda": null, "boost": null, "v": { "fp32": [ 67.0, null, "p" ], "fp64": [ 34.0, null, "p" ], "fp64tc": [ 67.0, null, "p" ], "tf32": [ 494.0, 989.0, "p" ], "fp16": [ 990.0, 1979.0, "p" ], "bf16": [ 990.0, 1979.0, "p" ], "fp8": [ 1979.0, 3958.0, "p" ], "int8": [ 1979.0, 3958.0, "p" ] }, "how": { "fp32": "NVIDIA: “FP32 67 teraFLOPS” [dam-cdn.nvd.orangelogic.com]", "fp64": "NVIDIA: “FP64 34 teraFLOPS” [dam-cdn.nvd.orangelogic.com]", "fp64tc": "NVIDIA: “FP64 Tensor Core 67 teraFLOPS” [dam-cdn.nvd.orangelogic.com]", "tf32": "NVIDIA: “TF32 Tensor Core 989 teraFLOPS* | 494 teraFLOPS (* With sparsity)” [dam-cdn.nvd.orangelogic.com]", "fp16": "NVIDIA: “FP16 Tensor Core 1,979 teraFLOPS* | 990 teraFLOPS” [dam-cdn.nvd.orangelogic.com]", "bf16": "NVIDIA: “BFLOAT16 Tensor Core 1,979 teraFLOPS* | 990 teraFLOPS” [dam-cdn.nvd.orangelogic.com]", "fp8": "NVIDIA: “FP8 Tensor Core 3,958 teraFLOPS* | 1,979 teraFLOPS” [dam-cdn.nvd.orangelogic.com]", "int8": "NVIDIA: “INT8 Tensor Core 3,958 TOPS* | 1,979 TOPS” [dam-cdn.nvd.orangelogic.com]" }, "na": { "fp6": "No FP6 tensor cores before Blackwell", "fp4": "No FP4 tensor cores before Blackwell", "int4": "Hopper dropped INT4 tensor support" }, "headline": null, "anchor": null, "notes": "Values are for one GH200 (one GPU), from the GH200 datasheet (MAR25). It also lists GH200 NVL2 (2 GPUs) at exactly double; that column's INT8 row is printed '7,916 teraFLOPS* | 3,958 teraFLOPS' (unit error). memory_gb, memory_type and bandwidth_gbs use the HBM3e variant; the HBM3 variant is 96 GB at up to 4 TB/s. tdp_w is the module range 450-1000 W for CPU + GPU + memory, not GPU-only. Dense values are rounded differently from the H100 whitepaper (TF32 494 vs 494.7; FP16/BF16 990 vs 989.4). Conflict: NVIDIA's 2022 Grace Hopper blog gives the Hopper GPU 'Up to 96 GB of HBM3 memory delivering up to 3000 GB/s' and 'Up to 144 SMs' (full GH100 die), versus the 2025 datasheet's 'Up to 4TB/s' for 96GB HBM3. NVIDIA does not publish GH200's enabled SM count or clocks.", "sources": [ { "t": "dam-cdn.nvd.orangelogic.com — /AssetLink/tkno03fa645gb7f33w60rf200d330420.pdf", "u": "https://dam-cdn.nvd.orangelogic.com/AssetLink/tkno03fa645gb7f33w60rf200d330420.pdf" }, { "t": "nvidia.com — /en-us/data-center/grace-hopper-superchip/", "u": "https://www.nvidia.com/en-us/data-center/grace-hopper-superchip/" }, { "t": "developer.nvidia.com — /blog/nvidia-grace-hopper-superchip-architecture-in-depth/", "u": "https://developer.nvidia.com/blog/nvidia-grace-hopper-superchip-architecture-in-depth/" } ], "aka": null }, { "id": "h100-nvl", "name": "NVIDIA H100 NVL", "short": "H100 NVL", "seg": "datacenter", "arch": "Hopper", "archGroup": "Hopper", "cls": "hopper", "clsLabel": "Hopper (H100, H200)", "chip": "GH100", "date": "2023-03", "t": 2023.1666666666667, "status": null, "ff": "PCIe Gen5 x16 card, FHFL 10.5 in, dual-slot, passive; NVLink bridge pairs", "mem": 94.0, "memType": "HBM3", "bw": 3938.0, "tdp": 400.0, "sms": null, "tc": null, "cuda": null, "boost": 1785.0, "v": { "fp32": [ 60.0, null, "p" ], "fp64": [ 30.0, null, "p" ], "fp64tc": [ 60.0, null, "p" ], "tf32": [ 417.5, 835.0, "p" ], "fp16": [ 835.5, 1671.0, "p" ], "bf16": [ 835.5, 1671.0, "p" ], "fp8": [ 1670.5, 3341.0, "p" ], "int8": [ 1670.5, 3341.0, "p" ] }, "how": { "fp32": "NVIDIA: “FP32 60 teraFLOPs” [nvidia.com]", "fp64": "NVIDIA: “FP64 30 teraFLOPs” [nvidia.com]", "fp64tc": "NVIDIA: “FP64 Tensor Core 60 teraFLOPs” [nvidia.com]", "tf32": "NVIDIA: “TF32 Tensor Core* 835 teraFLOPs (* With sparsity)” (dense = half the published sparse figure) [nvidia.com]", "fp16": "NVIDIA: “FP16 Tensor Core* 1,671 teraFLOPS” (dense = half the published sparse figure) [nvidia.com]", "bf16": "NVIDIA: “BFLOAT16 Tensor Core* 1,671 teraFLOPS” (dense = half the published sparse figure) [nvidia.com]", "fp8": "NVIDIA: “FP8 Tensor Core* 3,341 teraFLOPS” (dense = half the published sparse figure) [nvidia.com]", "int8": "NVIDIA: “INT8 Tensor Core* 3,341 TOPS” (dense = half the published sparse figure) [nvidia.com]" }, "na": { "fp6": "No FP6 tensor cores before Blackwell", "fp4": "No FP4 tensor cores before Blackwell", "int4": "Hopper dropped INT4 tensor support" }, "headline": null, "anchor": null, "notes": "Dense tensor figures are not published for H100 NVL. Page: TDP '350-400W (configurable)', bandwidth '3.9TB/s', 'Up to 7 MIGS @ 12GB each', NVLink 600GB/s. Revision conflict: NVIDIA's 2023 H100 page (web.archive.org 2023-06-01) listed H100 NVL as a pair ('Specifications shown for 2x H100 NVL PCIe cards paired with NVLink Bridge'; preliminary): FP64 68, FP64 Tensor Core 134, FP32 134, TF32² 1,979, BFLOAT16²/FP16² 3,958, FP8² 7,916 teraFLOPs, INT8² 7,916 TOPS, 188GB, 7.8TB/s, 2x 350-400W. Halved, that is 34/67/67/989.5 TFLOPS per card (H100 SXM level) versus the final per-card 30/60/60/835. NVIDIA does not publish the SM count.", "sources": [ { "t": "nvidia.com — /en-us/data-center/h100/", "u": "https://www.nvidia.com/en-us/data-center/h100/" }, { "t": "nvidia.com — /content/dam/en-zz/Solutions/Data-Center/h100/PB-11773-001_v01.pdf", "u": "https://www.nvidia.com/content/dam/en-zz/Solutions/Data-Center/h100/PB-11773-001_v01.pdf" }, { "t": "web.archive.org — /web/20230601203513/https://www.nvidia.com/en-us/data-center/h100/", "u": "http://web.archive.org/web/20230601203513/https://www.nvidia.com/en-us/data-center/h100/" } ], "aka": null }, { "id": "l4", "name": "NVIDIA L4", "short": "L4", "seg": "datacenter", "arch": "Ada", "archGroup": "Ada", "cls": "ada-pro", "clsLabel": "Ada (RTX Ada, L4, L40S)", "chip": "AD104", "date": "2023-03", "t": 2023.1666666666667, "status": null, "ff": "PCIe Gen4 x16, single-slot low-profile, passive", "mem": 24.0, "memType": "GDDR6", "bw": 300.0, "tdp": 72.0, "sms": 58.0, "tc": 232.0, "cuda": 7424.0, "boost": 2040.0, "v": { "fp32": [ 30.3, null, "p" ], "fp64": [ 0.4734, null, "d" ], "tf32": [ 60.0, 120.0, "p" ], "fp16": [ 121.0, 242.0, "p" ], "bf16": [ 121.0, 242.0, "p" ], "fp8": [ 242.0, 485.0, "p" ], "int8": [ 242.0, 485.0, "p" ], "int4": [ 484.0, 969.0, "p" ] }, "how": { "fp32": "NVIDIA: “Table 5: FP32 Performance 30.3 TFLOPS” [images.nvidia.com]", "fp64": "Derived: FP32 ÷ 64 (this architecture's FP64 rate)", "tf32": "NVIDIA: “Table 5: Tensor Float 32 (TF32) Performance 60 | 120 TFLOPS¹ (¹Effective TOPS / TFLOPS using the new Sparsity Feature)” [images.nvidia.com]", "fp16": "NVIDIA: “Table 5: FP16 Tensor Core Performance 121 | 242 TFLOPS¹” [images.nvidia.com]", "bf16": "NVIDIA: “Table 5: BFLOAT16 Tensor Core Performance 121 | 242 TFLOPS¹” [images.nvidia.com]", "fp8": "NVIDIA: “Table 5: FP8 Tensor Core Performance 242 | 485 TFLOPS¹” [images.nvidia.com]", "int8": "NVIDIA: “Table 5: INT8 Tensor Core Performance 242 | 485 TOPS¹” [images.nvidia.com]", "int4": "NVIDIA: “Table 5: INT4 Tensor Core Performance 484 | 969 TOPS¹” [images.nvidia.com]" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "fp6": "No FP6 tensor cores before Blackwell", "fp4": "No FP4 tensor cores before Blackwell" }, "headline": null, "anchor": "Derived from NVIDIA's published FP16 figure of 121 dense. ", "notes": "nvidia.com/l4 and the L4 datasheet (AUG24) give sparse tensor values only, matching the whitepaper: FP32 30.3 teraFLOPs; TF32 120*, FP16 242*, BFLOAT16 242*, FP8 485* teraFLOPS; INT8 485 TOPs* (page: '* Shown with sparsity. Specifications are one-half lower without sparsity.'; datasheet: 'Specifications 1/2 lower without sparsity.'). INT4 appears only in the Ada whitepaper V2.02, and its sparse 969 is not exactly 2x the dense 484 (rounding). No FP64 figure is published.", "sources": [ { "t": "images.nvidia.com — /aem-dam/Solutions/Data-Center/l4/nvidia-ada-gpu-architecture-whitepaper-V2.02.p", "u": "https://images.nvidia.com/aem-dam/Solutions/Data-Center/l4/nvidia-ada-gpu-architecture-whitepaper-V2.02.pdf" }, { "t": "nvidia.com — /en-us/data-center/l4/", "u": "https://www.nvidia.com/en-us/data-center/l4/" }, { "t": "dam-cdn.nvd.orangelogic.com — /AssetLink/8f4cjsr458mk07kxxt608b1ct0t570x7.pdf", "u": "https://dam-cdn.nvd.orangelogic.com/AssetLink/8f4cjsr458mk07kxxt608b1ct0t570x7.pdf" }, { "t": "nvidia.com — /content/dam/en-zz/Solutions/Data-Center/l4/PB-11316-001_v01.pdf", "u": "https://www.nvidia.com/content/dam/en-zz/Solutions/Data-Center/l4/PB-11316-001_v01.pdf" } ], "aka": null }, { "id": "l40", "name": "NVIDIA L40", "short": "L40", "seg": "datacenter", "arch": "Ada", "archGroup": "Ada", "cls": "ada-pro", "clsLabel": "Ada (RTX Ada, L4, L40S)", "chip": "AD102", "date": "2022-09", "t": 2022.6666666666667, "status": null, "ff": "PCIe Gen4 x16, FHFL 10.5 in, dual-slot, passive", "mem": 48.0, "memType": "GDDR6 (ECC)", "bw": 864.0, "tdp": 300.0, "sms": 142.0, "tc": 568.0, "cuda": 18176.0, "boost": 2490.0, "v": { "fp32": [ 90.5, null, "p" ], "fp64": [ 1.4141, null, "d" ], "tf32": [ 90.5, 181.0, "p" ], "fp16": [ 181.05, 362.1, "p" ], "bf16": [ 181.05, 362.1, "p" ], "fp8": [ 362.0, 724.0, "p" ], "int8": [ 362.0, 724.0, "p" ], "int4": [ 724.0, 1448.0, "p" ] }, "how": { "fp32": "NVIDIA: “FP32 TFLOPS 90.5” [images.nvidia.com]", "fp64": "Derived: FP32 ÷ 64 (this architecture's FP64 rate)", "tf32": "NVIDIA: “TF32 Tensor Core TFLOPS 90.5 | 181** (** With Sparsity.)” [images.nvidia.com]", "fp16": "NVIDIA: “FP16 Tensor Core 181.05 | 362.1**” [images.nvidia.com]", "bf16": "NVIDIA: “BFLOAT16 Tensor Core TFLOPS 181.05 | 362.1**” [images.nvidia.com]", "fp8": "NVIDIA: “FP8 Tensor Core 362 | 724**” [images.nvidia.com]", "int8": "NVIDIA: “Peak INT8 Tensor TOPS 362 | 724**” [images.nvidia.com]", "int4": "NVIDIA: “Peak INT4 Tensor TOPS 724 | 1448**” [images.nvidia.com]" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "fp6": "No FP6 tensor cores before Blackwell", "fp4": "No FP4 tensor cores before Blackwell" }, "headline": null, "anchor": "Derived from NVIDIA's published FP16 figure of 181.05 dense. ", "notes": "Datasheet table is headed 'Technical Specifications*' with '* Preliminary specifications, subject to change.' Ada whitepaper Table 4 rounds to TF32 90.5 | 181, BF16/FP16 181 | 362, FP8 362 | 724, INT8 362 | 724, INT4 724 | 1448 (sparse via footnote 1). RT Core performance: datasheet 209 TFLOPS vs whitepaper 209.3. Product brief PB-11131-001_v03 (January 2023) is marked 'PRELIMINARY INFORMATION'. nvidia.com/l40 lists no throughput figures. No FP64 figure is published.", "sources": [ { "t": "images.nvidia.com — /content/Solutions/data-center/vgpu-L40-datasheet.pdf", "u": "https://images.nvidia.com/content/Solutions/data-center/vgpu-L40-datasheet.pdf" }, { "t": "images.nvidia.com — /aem-dam/Solutions/Data-Center/l4/nvidia-ada-gpu-architecture-whitepaper-V2.02.p", "u": "https://images.nvidia.com/aem-dam/Solutions/Data-Center/l4/nvidia-ada-gpu-architecture-whitepaper-V2.02.pdf" }, { "t": "nvidia.com — /content/dam/en-zz/Solutions/Data-Center/datasheets/L-40/product-brief-L40.pdf", "u": "https://www.nvidia.com/content/dam/en-zz/Solutions/Data-Center/datasheets/L-40/product-brief-L40.pdf" }, { "t": "nvidia.com — /en-us/data-center/l40/", "u": "https://www.nvidia.com/en-us/data-center/l40/" } ], "aka": null }, { "id": "h100-pcie", "name": "NVIDIA H100 PCIe", "short": "H100 PCIe", "seg": "datacenter", "arch": "Hopper", "archGroup": "Hopper", "cls": "hopper", "clsLabel": "Hopper (H100, H200)", "chip": "GH100", "date": "2022-03", "t": 2022.1666666666667, "status": null, "ff": "PCIe Gen5 x16 card, FHFL 10.5 in, dual-slot, passive", "mem": 80.0, "memType": "HBM2e", "bw": 2000.0, "tdp": 350.0, "sms": 114.0, "tc": 456.0, "cuda": 14592.0, "boost": 1755.0, "v": { "fp32": [ 51.2, null, "p" ], "fp64": [ 25.6, null, "p" ], "fp64tc": [ 51.2, null, "p" ], "tf32": [ 378.0, 756.0, "p" ], "fp16": [ 756.0, 1513.0, "p" ], "bf16": [ 756.0, 1513.0, "p" ], "fp8": [ 1513.0, 3026.0, "p" ], "int8": [ 1513.0, 3026.0, "p" ] }, "how": { "fp32": "NVIDIA: “Table 1: Peak FP32 51.2 TFLOPS” [dam-cdn.nvd.orangelogic.com]", "fp64": "NVIDIA: “Table 1: Peak FP64 25.6 TFLOPS” [dam-cdn.nvd.orangelogic.com]", "fp64tc": "NVIDIA: “Table 1: Peak FP64 Tensor Core 51.2 TFLOPS” [dam-cdn.nvd.orangelogic.com]", "tf32": "NVIDIA: “Table 1: Peak TF32 Tensor Core 378 TFLOPS | 756 TFLOPS¹ (¹Effective TFLOPS / TOPS using the Sparsity feature)” [dam-cdn.nvd.orangelogic.com]", "fp16": "NVIDIA: “Table 3: Peak FP16 Tensor TFLOPS with FP32 Accumulate 756/1513¹” [dam-cdn.nvd.orangelogic.com]", "bf16": "NVIDIA: “Table 1: Peak BF16 Tensor Core 756 TFLOPS | 1513 TFLOPS² (footnote ² is undefined in the whitepaper; Table 3 gives 756/1513¹)” [dam-cdn.nvd.orangelogic.com]", "fp8": "NVIDIA: “Table 1: Peak FP8 Tensor Core 1513 TFLOPS | 3026 TFLOPS¹” [dam-cdn.nvd.orangelogic.com]", "int8": "NVIDIA: “Table 1: Peak INT8 Tensor Core 1513 TOPS | 3026 TOPS¹” [dam-cdn.nvd.orangelogic.com]" }, "na": { "fp6": "No FP6 tensor cores before Blackwell", "fp4": "No FP4 tensor cores before Blackwell", "int4": "Hopper dropped INT4 tensor support" }, "headline": null, "anchor": null, "notes": "The current nvidia.com/h100 page no longer lists H100 PCIe (only H100 SXM and H100 NVL). NVIDIA's 2023 H100 page (web.archive.org capture 2023-06-01, source_quality nvidia_archived) listed: FP64 26, FP64 Tensor Core 51, FP32 51 teraFLOPS; TF32² 756, BFLOAT16² 1,513, FP16² 1,513, FP8² 3,026 teraFLOPS; INT8² 3,026 TOPS (²With sparsity); 80GB; 2TB/s; Max TDP 300-350W (configurable). Whitepaper Table 3 instead gives Memory Bandwidth 2039 GB/sec and TDP 350 Watts. Product brief (file name _v01, content PB-11133-001_v02) says three NVLink bridges 'deliver 900 GB/s bidirectional bandwidth' in its overview but its Table 6 says 'Total maximum NVLink bandwidth 600 Gbytes per second' (2023 page also 600GB/s).", "sources": [ { "t": "dam-cdn.nvd.orangelogic.com — /AssetLink/705n6ur546g0uk43w0117r17n8042d73.pdf", "u": "https://dam-cdn.nvd.orangelogic.com/AssetLink/705n6ur546g0uk43w0117r17n8042d73.pdf" }, { "t": "nvidia.com — /content/dam/en-zz/Solutions/gtcs22/data-center/h100/PB-11133-001_v01.pdf", "u": "https://www.nvidia.com/content/dam/en-zz/Solutions/gtcs22/data-center/h100/PB-11133-001_v01.pdf" }, { "t": "web.archive.org — /web/20230601203513/https://www.nvidia.com/en-us/data-center/h100/", "u": "http://web.archive.org/web/20230601203513/https://www.nvidia.com/en-us/data-center/h100/" } ], "aka": null }, { "id": "h100-sxm5", "name": "NVIDIA H100 SXM", "short": "H100 SXM", "seg": "datacenter", "arch": "Hopper", "archGroup": "Hopper", "cls": "hopper", "clsLabel": "Hopper (H100, H200)", "chip": "GH100", "date": "2022-03", "t": 2022.1666666666667, "status": null, "ff": "SXM5 module (HGX H100 4-/8-GPU boards, DGX H100)", "mem": 80.0, "memType": "HBM3", "bw": 3350.0, "tdp": 700.0, "sms": 132.0, "tc": 528.0, "cuda": 16896.0, "boost": 1980.0, "v": { "fp32": [ 66.9, null, "p" ], "fp64": [ 33.5, null, "p" ], "fp64tc": [ 66.9, null, "p" ], "tf32": [ 494.7, 989.4, "p" ], "fp16": [ 989.4, 1978.9, "p" ], "bf16": [ 989.4, 1978.9, "p" ], "fp8": [ 1978.9, 3957.8, "p" ], "int8": [ 1978.9, 3957.8, "p" ] }, "how": { "fp32": "NVIDIA: “Table 1: Peak FP32 66.9 TFLOPS” [dam-cdn.nvd.orangelogic.com]", "fp64": "NVIDIA: “Table 1: Peak FP64 33.5 TFLOPS” [dam-cdn.nvd.orangelogic.com]", "fp64tc": "NVIDIA: “Table 1: Peak FP64 Tensor Core 66.9 TFLOPS” [dam-cdn.nvd.orangelogic.com]", "tf32": "NVIDIA: “Table 1: Peak TF32 Tensor Core 494.7 TFLOPS | 989.4 TFLOPS¹ (¹Effective TFLOPS / TOPS using the Sparsity feature)” [dam-cdn.nvd.orangelogic.com]", "fp16": "NVIDIA: “Table 3: Peak FP16 Tensor TFLOPS with FP32 Accumulate 989.4/1978.9¹” [dam-cdn.nvd.orangelogic.com]", "bf16": "NVIDIA: “Table 1: Peak BF16 Tensor Core 989.4 TFLOPS | 1978.9 TFLOPS¹” [dam-cdn.nvd.orangelogic.com]", "fp8": "NVIDIA: “Table 1: Peak FP8 Tensor Core 1978.9 TFLOPS | 3957.8 TFLOPS¹ (Table 3 gives the same for FP16 and FP32 accumulate)” [dam-cdn.nvd.orangelogic.com]", "int8": "NVIDIA: “Table 1: Peak INT8 Tensor Core 1978.9 TOPS | 3957.8 TOPS¹” [dam-cdn.nvd.orangelogic.com]" }, "na": { "fp6": "No FP6 tensor cores before Blackwell", "fp4": "No FP4 tensor cores before Blackwell", "int4": "Hopper dropped INT4 tensor support" }, "headline": null, "anchor": null, "notes": "nvidia.com/h100 (Oct 2026) gives the same figures rounded, sparse only: FP64 34, FP64 Tensor Core 67, FP32 67 teraFLOPS; TF32* 989, BFLOAT16* 1,979, FP16* 1,979, FP8* 3,958 teraFLOPS; INT8* 3,958 TOPS (*With sparsity). Whitepaper V1.04 says it 'Includes final GPU / memory clocks and final TFLOPS performance specs'. Tensor-op peaks are at 1830 MHz, FP64/FP32 peaks at 1980 MHz (Table 3 footnote 2: GPU Peak Clock and GPU Boost Clock are synonymous). HGX H100 8-GPU datasheet (Jul24) totals, sparse*: FP8 32 PFLOPS, INT8 32 POPS, FP16/BF16 16 PFLOPS, TF32 8 PFLOPS; FP32 540, FP64 270, FP64 Tensor Core 540 TFLOPS (rounded; 270/8 = 33.75). That datasheet prints the 8-GPU aggregate bandwidth as '27GB/s' (typo for TB/s). Whitepaper Table 3 still labels the bandwidth row 'Memory Bandwidth (Not Finalized for H100)'.", "sources": [ { "t": "dam-cdn.nvd.orangelogic.com — /AssetLink/705n6ur546g0uk43w0117r17n8042d73.pdf", "u": "https://dam-cdn.nvd.orangelogic.com/AssetLink/705n6ur546g0uk43w0117r17n8042d73.pdf" }, { "t": "nvidia.com — /en-us/data-center/h100/", "u": "https://www.nvidia.com/en-us/data-center/h100/" }, { "t": "dam-cdn.nvd.orangelogic.com — /AssetLink/44wa8u63l12ps4ie2870214xa2exoyra.pdf", "u": "https://dam-cdn.nvd.orangelogic.com/AssetLink/44wa8u63l12ps4ie2870214xa2exoyra.pdf" } ], "aka": null }, { "id": "a2", "name": "NVIDIA A2", "short": "A2", "seg": "datacenter", "arch": "Ampere", "archGroup": "Ampere", "cls": "ampere-pro", "clsLabel": "Ampere GA10x (RTX A, A10, A40)", "chip": "GA107", "date": "2021-11", "t": 2021.8333333333333, "status": null, "ff": "PCIe Gen4 x8, single-slot low-profile half-length (HHHL), passive", "mem": 16.0, "memType": "GDDR6", "bw": 200.0, "tdp": 60.0, "sms": null, "tc": null, "cuda": null, "boost": 1770.0, "v": { "fp32": [ 4.5, null, "p" ], "fp64": [ 0.0703, null, "d" ], "tf32": [ 9.0, 18.0, "p" ], "fp16": [ 18.0, 36.0, "p" ], "bf16": [ 18.0, 36.0, "p" ], "int8": [ 36.0, 72.0, "p" ], "int4": [ 72.0, 144.0, "p" ] }, "how": { "fp32": "NVIDIA: “Peak FP32: 4.5 TF” [nvidia.com]", "fp64": "Derived: FP32 ÷ 64 (this architecture's FP64 rate)", "tf32": "NVIDIA: “TF32 Tensor Core: 9 TF | 18 TF¹” [nvidia.com]", "fp16": "NVIDIA: “Peak FP16 Tensor Core: 18 TF | 36 TF¹” [nvidia.com]", "bf16": "NVIDIA: “BFLOAT16 Tensor Core: 18 TF | 36 TF¹” [nvidia.com]", "int8": "NVIDIA: “Peak INT8 Tensor Core: 36 TOPS | 72 TOPS¹” [nvidia.com]", "int4": "NVIDIA: “Peak INT4 Tensor Core: 72 TOPS | 144 TOPS¹” [nvidia.com]" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "fp8": "No FP8 tensor cores before Ada/Hopper (FP8 models run at FP16 speed)", "fp6": "No FP6 tensor cores before Blackwell", "fp4": "No FP4 tensor cores before Blackwell" }, "headline": null, "anchor": "Derived from NVIDIA's published FP16 figure of 18 dense. ", "notes": "Footnote '¹ With sparsity'. TDP is configurable from 40 to 60 W; NVIDIA does not say which power level the peaks assume (tdp_w records the 60 W default/maximum). NVIDIA lists 10 RT Cores but no SM, Tensor-core or CUDA-core counts, so those are null. No FP64 figure is published. The FP16 Tensor figure does not state accumulate precision. The product brief gives memory clock 6251 MHz and a 128-bit bus.", "sources": [ { "t": "nvidia.com — /content/dam/en-zz/solutions/data-center/a2/pdf/a2-datasheet.pdf", "u": "https://www.nvidia.com/content/dam/en-zz/solutions/data-center/a2/pdf/a2-datasheet.pdf" }, { "t": "nvidia.com — /content/dam/en-zz/solutions/data-center/a2/pdf/a2-product-brief.pdf", "u": "https://www.nvidia.com/content/dam/en-zz/solutions/data-center/a2/pdf/a2-product-brief.pdf" }, { "t": "nvidia.com — /en-us/data-center/products/a2/", "u": "https://www.nvidia.com/en-us/data-center/products/a2/" }, { "t": "techpowerup.com — /gpu-specs/a2-pcie.c3848", "u": "https://www.techpowerup.com/gpu-specs/a2-pcie.c3848" } ], "aka": "A2 A2 PCIe" }, { "id": "a100-pcie-80gb", "name": "NVIDIA A100 80GB PCIe", "short": "A100 80GB PCIe", "seg": "datacenter", "arch": "Ampere", "archGroup": "Ampere", "cls": "ampere-ga100", "clsLabel": "Ampere GA100 (A100, A30)", "chip": "GA100", "date": "2021-06", "t": 2021.4166666666667, "status": null, "ff": "PCIe Gen4 x16, full-height full-length dual-slot 10.5 in air-cooled (passive); the May22 datasheet also lists a single-slot liquid-cooled version", "mem": 80.0, "memType": "HBM2e", "bw": 1935.0, "tdp": 300.0, "sms": 108.0, "tc": 432.0, "cuda": 6912.0, "boost": 1410.0, "v": { "fp32": [ 19.5, null, "p" ], "fp64": [ 9.7, null, "p" ], "fp64tc": [ 19.5, null, "p" ], "tf32": [ 156.0, 312.0, "p" ], "fp16": [ 312.0, 624.0, "p" ], "bf16": [ 312.0, 624.0, "p" ], "int8": [ 624.0, 1248.0, "p" ], "int4": [ 1248.0, 2496.0, "d" ] }, "how": { "fp32": "NVIDIA: “FP32: 19.5 TFLOPS” [nvidia.com]", "fp64": "NVIDIA: “FP64: 9.7 TFLOPS” [nvidia.com]", "fp64tc": "NVIDIA: “FP64 Tensor Core: 19.5 TFLOPS” [nvidia.com]", "tf32": "NVIDIA: “Tensor Float 32 (TF32): 156 TFLOPS | 312 TFLOPS*” [nvidia.com]", "fp16": "NVIDIA: “FP16 Tensor Core: 312 TFLOPS | 624 TFLOPS*” [nvidia.com]", "bf16": "NVIDIA: “BFLOAT16 Tensor Core: 312 TFLOPS | 624 TFLOPS*” [nvidia.com]", "int8": "NVIDIA: “INT8 Tensor Core: 624 TOPS | 1248 TOPS*” [nvidia.com]", "int4": "Derived from NVIDIA's published FP16 figure of 312 dense. On GA100, INT4 runs at 4× the FP16 rate" }, "na": { "fp8": "No FP8 tensor cores before Ada/Hopper (FP8 models run at FP16 speed)", "fp6": "No FP6 tensor cores before Blackwell", "fp4": "No FP4 tensor cores before Blackwell" }, "headline": null, "anchor": "Derived from NVIDIA's published FP16 figure of 312 dense. ", "notes": "No INT4 figure was published for this SKU in any NVIDIA document found (Jun21 and May22 datasheets, product brief, product page). It is left absent rather than copied from the 40GB card. The product brief says 'Up to 1.94 TB/s' and the datasheets say 1,935GB/s (rounding). The product brief gives TDP as 300 W default, 300 W maximum, 150 W minimum, with memory clock 1512 MHz and a 5120-bit bus. The product brief URL says v02, but the downloaded document is PB-10577-001_v03 (March 2022).", "sources": [ { "t": "nvidia.com — /content/dam/en-zz/Solutions/Data-Center/a100/pdf/nvidia-a100-datasheet-nvidia-u", "u": "https://www.nvidia.com/content/dam/en-zz/Solutions/Data-Center/a100/pdf/nvidia-a100-datasheet-nvidia-us-2188504-web.pdf" }, { "t": "nvidia.com — /content/dam/en-zz/Solutions/Data-Center/a100/pdf/nvidia-a100-datasheet-us-nvidi", "u": "https://www.nvidia.com/content/dam/en-zz/Solutions/Data-Center/a100/pdf/nvidia-a100-datasheet-us-nvidia-1758950-r4-web.pdf" }, { "t": "nvidia.com — /content/dam/en-zz/Solutions/Data-Center/a100/pdf/PB-10577-001_v02.pdf", "u": "https://www.nvidia.com/content/dam/en-zz/Solutions/Data-Center/a100/pdf/PB-10577-001_v02.pdf" }, { "t": "nvidia.com — /en-us/data-center/a100/", "u": "https://www.nvidia.com/en-us/data-center/a100/" }, { "t": "images.nvidia.com — /aem-dam/en-zz/Solutions/data-center/nvidia-ampere-architecture-whitepaper.pdf", "u": "https://images.nvidia.com/aem-dam/en-zz/Solutions/data-center/nvidia-ampere-architecture-whitepaper.pdf" } ], "aka": "A100 PCIe 80GB" }, { "id": "a10", "name": "NVIDIA A10", "short": "A10", "seg": "datacenter", "arch": "Ampere", "archGroup": "Ampere", "cls": "ampere-pro", "clsLabel": "Ampere GA10x (RTX A, A10, A40)", "chip": "GA102", "date": "2021-04", "t": 2021.25, "status": null, "ff": "PCIe Gen4 x16, single-slot full-height full-length (1-slot FHFL) 10.5 in, passive", "mem": 24.0, "memType": "GDDR6", "bw": 600.0, "tdp": 150.0, "sms": null, "tc": null, "cuda": null, "boost": 1695.0, "v": { "fp32": [ 31.2, null, "p" ], "fp64": [ 0.4875, null, "d" ], "tf32": [ 62.5, 125.0, "p" ], "fp16": [ 125.0, 250.0, "p" ], "bf16": [ 125.0, 250.0, "p" ], "int8": [ 250.0, 500.0, "p" ], "int4": [ 500.0, 1000.0, "p" ] }, "how": { "fp32": "NVIDIA: “FP32: 31.2 TF” [nvidia.com]", "fp64": "Derived: FP32 ÷ 64 (this architecture's FP64 rate)", "tf32": "NVIDIA: “TF32 Tensor Core: 62.5 TF | 125 TF*” [nvidia.com]", "fp16": "NVIDIA: “FP16 Tensor Core: 125 TF | 250 TF*” [nvidia.com]", "bf16": "NVIDIA: “BFLOAT16 Tensor Core: 125 TF | 250 TF*” [nvidia.com]", "int8": "NVIDIA: “INT8 Tensor Core: 250 TOPS | 500 TOPS*” [nvidia.com]", "int4": "NVIDIA: “INT4 Tensor Core: 500 TOPS | 1000 TOPS*” [nvidia.com]" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "fp8": "No FP8 tensor cores before Ada/Hopper (FP8 models run at FP16 speed)", "fp6": "No FP6 tensor cores before Blackwell", "fp4": "No FP4 tensor cores before Blackwell" }, "headline": null, "anchor": "Derived from NVIDIA's published FP16 figure of 125 dense. ", "notes": "Footnote '*with sparsity'. The Mar21 and Mar22 datasheets have identical throughput. No FP64 figure is published. The FP16 Tensor figure does not say which accumulate precision it uses; whether FP32 accumulate runs at full rate on A10 is unpublished (see open_questions). NVIDIA lists 72 RT Cores but no SM, Tensor-core or CUDA-core counts, so those are null. The product brief gives memory clock 6251 MHz and a 384-bit bus.", "sources": [ { "t": "nvidia.com — /content/dam/en-zz/Solutions/Data-Center/a10/pdf/datasheet-new/nvidia-a10-datash", "u": "https://www.nvidia.com/content/dam/en-zz/Solutions/Data-Center/a10/pdf/datasheet-new/nvidia-a10-datasheet.pdf" }, { "t": "nvidia.com — /content/dam/en-zz/Solutions/Data-Center/a10/pdf/a10-datasheet.pdf", "u": "https://www.nvidia.com/content/dam/en-zz/Solutions/Data-Center/a10/pdf/a10-datasheet.pdf" }, { "t": "nvidia.com — /content/dam/en-zz/Solutions/Data-Center/a10/pdf/A10-Product-Brief.pdf", "u": "https://www.nvidia.com/content/dam/en-zz/Solutions/Data-Center/a10/pdf/A10-Product-Brief.pdf" }, { "t": "nvidia.com — /en-us/data-center/products/a10-gpu/", "u": "https://www.nvidia.com/en-us/data-center/products/a10-gpu/" } ], "aka": "A10 A10 PCIe" }, { "id": "a16", "name": "NVIDIA A16 (per GPU; 4 per board)", "short": "A16 (per GPU)", "seg": "datacenter", "arch": "Ampere", "archGroup": "Ampere", "cls": "ampere-pro", "clsLabel": "Ampere GA10x (RTX A, A10, A40)", "chip": "GA107", "date": "2021-04", "t": 2021.25, "status": null, "ff": "PCIe Gen4 x16, full-height full-length dual-slot 10.5 in, passive; quad-GPU board", "mem": 16.0, "memType": "GDDR6", "bw": 200.0, "tdp": 62.5, "sms": null, "tc": 40.0, "cuda": 1280.0, "boost": 1755.0, "v": { "fp32": [ 4.5, null, "p" ], "fp64": [ 0.0703, null, "d" ], "tf32": [ 9.0, 18.0, "p" ], "fp16": [ 17.9, 35.9, "p" ], "bf16": [ 17.9, 35.8, "d" ], "int8": [ 35.9, 71.8, "p" ], "int4": [ 71.6, 143.2, "d" ] }, "how": { "fp32": "NVIDIA: “FP32 | TF32 | TF32¹ (TFLOPS): 4x 4.5 | 4x 9 | 4x 18” [images.nvidia.com]", "fp64": "Derived: FP32 ÷ 64 (this architecture's FP64 rate)", "tf32": "NVIDIA: “FP32 | TF32 | TF32¹ (TFLOPS): 4x 4.5 | 4x 9 | 4x 18” [images.nvidia.com]", "fp16": "NVIDIA: “FP16 | FP16¹ (TFLOPS): 4x 17.9 | 4x 35.9” [images.nvidia.com]", "bf16": "Derived from NVIDIA's published FP16 figure of 17.9 dense. On workstation and data-centre Ampere, BF16 runs at the same rate as FP16", "int8": "NVIDIA: “INT8 | INT8¹ (TOPS): 4x 35.9 | 4x 71.8” [images.nvidia.com]", "int4": "Derived from NVIDIA's published FP16 figure of 17.9 dense. On workstation and data-centre Ampere, INT4 runs at 4× the FP16 rate" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "fp8": "No FP8 tensor cores before Ada/Hopper (FP8 models run at FP16 speed)", "fp6": "No FP6 tensor cores before Blackwell", "fp4": "No FP4 tensor cores before Blackwell" }, "headline": null, "anchor": "Derived from NVIDIA's published FP16 figure of 17.9 dense. ", "notes": "NVIDIA lists the A16's throughput per GPU ('4x ...'); the board holds 4 separate GPUs with 16 GB each (64 GB total) and draws 250 W, so power here is a quarter of the board's.", "sources": [ { "t": "images.nvidia.com — /content/Solutions/data-center/vgpu-a16-datasheet.pdf", "u": "https://images.nvidia.com/content/Solutions/data-center/vgpu-a16-datasheet.pdf" }, { "t": "images.nvidia.com — /content/Solutions/data-center/vgpu-a16-product-brief.pdf", "u": "https://images.nvidia.com/content/Solutions/data-center/vgpu-a16-product-brief.pdf" }, { "t": "nvidia.com — /en-us/data-center/products/a16-gpu/", "u": "https://www.nvidia.com/en-us/data-center/products/a16-gpu/" } ], "aka": "A16 PCIe" }, { "id": "a30", "name": "NVIDIA A30", "short": "A30", "seg": "datacenter", "arch": "Ampere", "archGroup": "Ampere", "cls": "ampere-ga100", "clsLabel": "Ampere GA100 (A100, A30)", "chip": "GA100", "date": "2021-04", "t": 2021.25, "status": null, "ff": "PCIe Gen4 x16, 2-slot full-height full-length (FHFL) 10.5 in, passive; NVLink bridge for 2 GPUs (200 GB/s)", "mem": 24.0, "memType": "HBM2", "bw": 933.0, "tdp": 165.0, "sms": null, "tc": null, "cuda": null, "boost": 1440.0, "v": { "fp32": [ 10.3, null, "p" ], "fp64": [ 5.2, null, "p" ], "fp64tc": [ 10.3, null, "p" ], "tf32": [ 82.0, 165.0, "p" ], "fp16": [ 165.0, 330.0, "p" ], "bf16": [ 165.0, 330.0, "p" ], "int8": [ 330.0, 661.0, "p" ], "int4": [ 661.0, 1321.0, "p" ] }, "how": { "fp32": "NVIDIA: “Peak FP32: 10.3 TF” [nvidia.com]", "fp64": "NVIDIA: “Peak FP64: 5.2TF” [nvidia.com]", "fp64tc": "NVIDIA: “Peak FP64 Tensor Core: 10.3 TF” [nvidia.com]", "tf32": "NVIDIA: “TF32 Tensor Core: 82 TF | 165 TF*” [nvidia.com]", "fp16": "NVIDIA: “Peak FP16 Tensor Core: 165 TF | 330 TF*” [nvidia.com]", "bf16": "NVIDIA: “BFLOAT16 Tensor Core: 165 TF | 330 TF*” [nvidia.com]", "int8": "NVIDIA: “Peak INT8 Tensor Core: 330 TOPS | 661 TOPS*” [nvidia.com]", "int4": "NVIDIA: “Peak INT4 Tensor Core: 661 TOPS | 1321 TOPS*” [nvidia.com]" }, "na": { "fp8": "No FP8 tensor cores before Ada/Hopper (FP8 models run at FP16 speed)", "fp6": "No FP6 tensor cores before Blackwell", "fp4": "No FP4 tensor cores before Blackwell" }, "headline": null, "anchor": "Derived from NVIDIA's published FP16 figure of 165 dense. ", "notes": "Footnote: '* With sparsity'. CONFLICT (prose vs table): the datasheet prose says 'NVIDIA A30 delivers 165 teraFLOPS (TFLOPS) of TF32 deep learning performance', which is the sparse TF32 figure without the sparsity qualifier. The table gives 82 TF dense | 165 TF sparse, and the prose's '330 TFLOPs' for two NVLinked A30s also uses sparse figures. NVIDIA publishes no SM, Tensor-core or CUDA-core counts for A30, so they are left null. TechPowerUp's page is bot-protected; its meta summary lists 3584 cores, but CUDA cores are outside the permitted TechPowerUp fields. The product brief gives memory clock 1215 MHz and a 3072-bit bus. Product page uses 'teraFLOPS'; values are identical. Rounding is kept as printed: the sparse figures are not exactly 2x dense (TF32 82 | 165, INT8 330 | 661, INT4 661 | 1321).", "sources": [ { "t": "nvidia.com — /content/dam/en-zz/Solutions/data-center/products/a30-gpu/pdf/a30-datasheet.pdf", "u": "https://www.nvidia.com/content/dam/en-zz/Solutions/data-center/products/a30-gpu/pdf/a30-datasheet.pdf" }, { "t": "nvidia.com — /content/dam/en-zz/Solutions/data-center/products/a30-gpu/pdf/a30-product-brief.", "u": "https://www.nvidia.com/content/dam/en-zz/Solutions/data-center/products/a30-gpu/pdf/a30-product-brief.pdf" }, { "t": "nvidia.com — /en-us/data-center/products/a30-gpu/", "u": "https://www.nvidia.com/en-us/data-center/products/a30-gpu/" }, { "t": "techpowerup.com — /gpu-specs/a30-pcie.c3792", "u": "https://www.techpowerup.com/gpu-specs/a30-pcie.c3792" } ], "aka": "A30 A30 PCIe" }, { "id": "a100-sxm4-80gb", "name": "NVIDIA A100 80GB SXM", "short": "A100 80GB SXM", "seg": "datacenter", "arch": "Ampere", "archGroup": "Ampere", "cls": "ampere-ga100", "clsLabel": "Ampere GA100 (A100, A30)", "chip": "GA100", "date": "2020-11", "t": 2020.8333333333333, "status": null, "ff": "SXM4 module (HGX A100 4/8/16-GPU boards; NVLink 600 GB/s)", "mem": 80.0, "memType": "HBM2e", "bw": 2039.0, "tdp": 400.0, "sms": 108.0, "tc": 432.0, "cuda": 6912.0, "boost": 1410.0, "v": { "fp32": [ 19.5, null, "p" ], "fp64": [ 9.7, null, "p" ], "fp64tc": [ 19.5, null, "p" ], "tf32": [ 156.0, 312.0, "p" ], "fp16": [ 312.0, 624.0, "p" ], "bf16": [ 312.0, 624.0, "p" ], "int8": [ 624.0, 1248.0, "p" ], "int4": [ 1248.0, 2496.0, "p" ] }, "how": { "fp32": "NVIDIA: “FP32: 19.5 TFLOPS” [nvidia.com]", "fp64": "NVIDIA: “FP64: 9.7 TFLOPS” [nvidia.com]", "fp64tc": "NVIDIA: “FP64 Tensor Core: 19.5 TFLOPS” [nvidia.com]", "tf32": "NVIDIA: “Tensor Float 32 (TF32): 156 TFLOPS | 312 TFLOPS*” [nvidia.com]", "fp16": "NVIDIA: “FP16 Tensor Core: 312 TFLOPS | 624 TFLOPS*” [nvidia.com]", "bf16": "NVIDIA: “BFLOAT16 Tensor Core: 312 TFLOPS | 624 TFLOPS*” [nvidia.com]", "int8": "NVIDIA: “INT8 Tensor Core: 624 TOPS | 1248 TOPS*” [nvidia.com]", "int4": "NVIDIA: “Peak INT4 Tensor Core: 1,248 TOPS | 2,496 TOPS*” [nvidia.com]" }, "na": { "fp8": "No FP8 tensor cores before Ada/Hopper (FP8 models run at FP16 speed)", "fp6": "No FP6 tensor cores before Blackwell", "fp4": "No FP4 tensor cores before Blackwell" }, "headline": null, "anchor": "Derived from NVIDIA's published FP16 figure of 312 dense. ", "notes": "INT4 is published only in the Jan21 datasheet update (1521051-r2, 'NVIDIA A100 for NVLink' with 40GB and 80GB sub-columns); later datasheets dropped the row. The Jan21 datasheet also gives 2,039 GB/s and 400 W for the 80GB SXM. The HGX A100-80GB CTS SKU allows TDP up to 500 W with no change to the published peaks.", "sources": [ { "t": "nvidia.com — /content/dam/en-zz/Solutions/Data-Center/a100/pdf/nvidia-a100-datasheet-nvidia-u", "u": "https://www.nvidia.com/content/dam/en-zz/Solutions/Data-Center/a100/pdf/nvidia-a100-datasheet-nvidia-us-2188504-web.pdf" }, { "t": "nvidia.com — /content/dam/en-zz/Solutions/Data-Center/a100/pdf/nvidia-a100-datasheet-us-nvidi", "u": "https://www.nvidia.com/content/dam/en-zz/Solutions/Data-Center/a100/pdf/nvidia-a100-datasheet-us-nvidia-1758950-r4-web.pdf" }, { "t": "nvidia.com — /content/dam/en-zz/Solutions/Data-Center/a100/pdf/a100-80gb-datasheet-update-nvi", "u": "https://www.nvidia.com/content/dam/en-zz/Solutions/Data-Center/a100/pdf/a100-80gb-datasheet-update-nvidia-us-1521051-r2-web.pdf" }, { "t": "nvidia.com — /en-us/data-center/a100/", "u": "https://www.nvidia.com/en-us/data-center/a100/" }, { "t": "images.nvidia.com — /aem-dam/en-zz/Solutions/data-center/nvidia-ampere-architecture-whitepaper.pdf", "u": "https://images.nvidia.com/aem-dam/en-zz/Solutions/data-center/nvidia-ampere-architecture-whitepaper.pdf" }, { "t": "techpowerup.com — /gpu-specs/a100-sxm4-80-gb.c3746", "u": "https://www.techpowerup.com/gpu-specs/a100-sxm4-80-gb.c3746" } ], "aka": "A100 SXM4 80GB NVIDIA A100 for NVLink 80GB" }, { "id": "a40", "name": "NVIDIA A40", "short": "A40", "seg": "datacenter", "arch": "Ampere", "archGroup": "Ampere", "cls": "ampere-pro", "clsLabel": "Ampere GA10x (RTX A, A10, A40)", "chip": "GA102", "date": "2020-10", "t": 2020.75, "status": null, "ff": "PCIe Gen4 x16, 4.4 in (H) x 10.5 in (L) dual-slot, passive; NVLink bridge for 2 GPUs (112.5 GB/s)", "mem": 48.0, "memType": "GDDR6 (ECC)", "bw": 696.0, "tdp": 300.0, "sms": 84.0, "tc": 336.0, "cuda": 10752.0, "boost": 1740.0, "v": { "fp32": [ 37.4, null, "p" ], "fp64": [ 0.5844, null, "d" ], "tf32": [ 74.8, 149.6, "p" ], "fp16": [ 149.7, 299.4, "p" ], "bf16": [ 149.7, 299.4, "p" ], "int8": [ 299.3, 598.6, "p" ], "int4": [ 598.7, 1197.4, "p" ] }, "how": { "fp32": "NVIDIA: “Peak FP32 TFLOPS (non-Tensor): 37.4” [images.nvidia.com]", "fp64": "Derived: FP32 ÷ 64 (this architecture's FP64 rate)", "tf32": "NVIDIA: “Peak TF32 Tensor TFLOPS: 74.8 | 149.6*” [images.nvidia.com]", "fp16": "NVIDIA: “Peak FP16 Tensor TFLOPS with FP32 Accumulate¹: 149.7/299.4²” [nvidia.com]", "bf16": "NVIDIA: “Peak BF16 Tensor TFLOPS with FP32 Accumulate: 149.7 | 299.4*” [images.nvidia.com]", "int8": "NVIDIA: “Peak INT8 Tensor TOPS: 299.3 | 598.6*” [images.nvidia.com]", "int4": "NVIDIA: “Peak INT 4 Tensor TOPS: 598.7 | 1,197.4*” [images.nvidia.com]" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "fp8": "No FP8 tensor cores before Ada/Hopper (FP8 models run at FP16 speed)", "fp6": "No FP6 tensor cores before Blackwell", "fp4": "No FP4 tensor cores before Blackwell" }, "headline": null, "anchor": "Derived from NVIDIA's published FP16 figure of 149.7 dense. ", "notes": "Footnote '* Structural sparsity enabled'. The datasheet lists FP16 Tensor only with FP16 accumulate. GA102 whitepaper Table 3 adds FP16 Tensor with FP32 accumulate at the same 149.7/299.4 (full rate on A40, unlike GeForce GA102). Published rounding is kept as printed: TF32 dense 74.8 vs FP16 dense 149.7, and INT8 sparse 598.6 vs INT4 dense 598.7. Rates with no schema key: non-tensor FP16 and BF16 37.4 TFLOPS each, INT32 18.7 TOPS (whitepaper), and 'RT Core performance TFLOPS 73.1' (datasheet). The product brief prints units as 'Up to 696 GiB/s' and '48 GiB'; the datasheet and whitepaper say 696 GB/s and 48 GB. Launch month: NVIDIA's Q3 FY2021 results release (quarter ended Oct 2020) says it 'Introduced the NVIDIA RTX A6000 and NVIDIA A40 GPUs'. October 2020 is the GTC keynote month; NVIDIA's text confirms only the quarter.", "sources": [ { "t": "images.nvidia.com — /content/Solutions/data-center/a40/nvidia-a40-datasheet.pdf", "u": "https://images.nvidia.com/content/Solutions/data-center/a40/nvidia-a40-datasheet.pdf" }, { "t": "nvidia.com — /content/PDF/nvidia-ampere-ga-102-gpu-architecture-whitepaper-v2.pdf", "u": "https://www.nvidia.com/content/PDF/nvidia-ampere-ga-102-gpu-architecture-whitepaper-v2.pdf" }, { "t": "nvidia.com — /content/dam/en-zz/Solutions/Data-Center/a40/NVIDIA%20A40%20Product%20Brief.pdf", "u": "https://www.nvidia.com/content/dam/en-zz/Solutions/Data-Center/a40/NVIDIA%20A40%20Product%20Brief.pdf" }, { "t": "nvidia.com — /en-us/data-center/a40/", "u": "https://www.nvidia.com/en-us/data-center/a40/" }, { "t": "nvidianews.nvidia.com — /news/nvidia-announces-financial-results-for-third-quarter-fiscal-2021", "u": "https://nvidianews.nvidia.com/news/nvidia-announces-financial-results-for-third-quarter-fiscal-2021" } ], "aka": "A40 PCIe", "measured": { "best": { "fp32": { "value": 23.31, "unit": "TFLOPS", "sm_mhz": 1395.0, "power_w": 297.15999999999997 }, "tf32": { "value": 58.19, "unit": "TFLOPS", "sm_mhz": 1440.0, "power_w": 299.71000000000004 }, "fp16": { "value": 118.11, "unit": "TFLOPS", "sm_mhz": 1380.0, "power_w": 299.2 }, "fp16_acc16": { "value": 117.85, "unit": "TFLOPS", "sm_mhz": 1410.0, "power_w": 300.44 }, "bf16": { "value": 122.04, "unit": "TFLOPS", "sm_mhz": 1440.0, "power_w": 299.2 }, "int8": { "value": 227.06, "unit": "TOPS", "sm_mhz": 1395.0, "power_w": 300.15 }, "fp64": { "value": 0.5, "unit": "TFLOPS", "sm_mhz": 1740.0, "power_w": 134.24 }, "dram": { "value": 562.97, "unit": "GB/s", "sm_mhz": 1740.0, "power_w": 212.93 } } } }, { "id": "a100-pcie-40gb", "name": "NVIDIA A100 40GB PCIe", "short": "A100 40GB PCIe", "seg": "datacenter", "arch": "Ampere", "archGroup": "Ampere", "cls": "ampere-ga100", "clsLabel": "Ampere GA100 (A100, A30)", "chip": "GA100", "date": "2020-06", "t": 2020.4166666666667, "status": null, "ff": "PCIe Gen4 x16, full-height full-length dual-slot 10.5 in, passive (NVLink bridge for 2 GPUs)", "mem": 40.0, "memType": "HBM2", "bw": 1555.0, "tdp": 250.0, "sms": 108.0, "tc": 432.0, "cuda": 6912.0, "boost": 1410.0, "v": { "fp32": [ 19.5, null, "p" ], "fp64": [ 9.7, null, "p" ], "fp64tc": [ 19.5, null, "p" ], "tf32": [ 156.0, 312.0, "p" ], "fp16": [ 312.0, 624.0, "p" ], "bf16": [ 312.0, 624.0, "p" ], "int8": [ 624.0, 1248.0, "p" ], "int4": [ 1248.0, 2496.0, "p" ] }, "how": { "fp32": "NVIDIA: “FP32: 19.5 TFLOPS” [nvidia.com]", "fp64": "NVIDIA: “FP64: 9.7 TFLOPS” [nvidia.com]", "fp64tc": "NVIDIA: “FP64 Tensor Core: 19.5 TFLOPS” [nvidia.com]", "tf32": "NVIDIA: “Tensor Float 32 (TF32): 156 TFLOPS | 312 TFLOPS*” [nvidia.com]", "fp16": "NVIDIA: “FP16 Tensor Core: 312 TFLOPS | 624 TFLOPS*” [nvidia.com]", "bf16": "NVIDIA: “BFLOAT16 Tensor Core: 312 TFLOPS | 624 TFLOPS*” [nvidia.com]", "int8": "NVIDIA: “INT8 Tensor Core: 624 TOPS | 1248 TOPS*” [nvidia.com]", "int4": "NVIDIA: “Integer Performance ... INT4: 1,248 TOPS | 2,496 TOPS*” [nvidia.com]" }, "na": { "fp8": "No FP8 tensor cores before Ada/Hopper (FP8 models run at FP16 speed)", "fp6": "No FP6 tensor cores before Blackwell", "fp4": "No FP4 tensor cores before Blackwell" }, "headline": null, "anchor": "Derived from NVIDIA's published FP16 figure of 312 dense. ", "notes": "Sparse values are the '*' figures; footnotes read '* With sparsity' (Jun21) and '* Structural sparsity enabled' (Jun20). INT4 appears in the Jun20 and Jan21 datasheets but not the Jun21 datasheet. CONFLICT (rounding): the Jun20 datasheet gives 'Memory Bandwidth 1.6 TB/sec'; the product brief ('Up to 1555 GB/s'), whitepaper and later datasheets give 1,555 GB/s. The Jun20 datasheet also lists 'Delivered Performance for Top Apps' as 100% for HGX vs 90% for PCIe, despite identical peak specs. The product brief lists memory clock 1215 MHz and a 5120-bit bus. SM/core counts come from the whitepaper's A100 product description, which is not specific to a form factor.", "sources": [ { "t": "nvidia.com — /content/dam/en-zz/Solutions/Data-Center/a100/pdf/nvidia-a100-datasheet-us-nvidi", "u": "https://www.nvidia.com/content/dam/en-zz/Solutions/Data-Center/a100/pdf/nvidia-a100-datasheet-us-nvidia-1758950-r4-web.pdf" }, { "t": "nvidia.com — /content/dam/en-zz/Solutions/Data-Center/a100/pdf/nvidia-a100-datasheet.pdf", "u": "https://www.nvidia.com/content/dam/en-zz/Solutions/Data-Center/a100/pdf/nvidia-a100-datasheet.pdf" }, { "t": "nvidia.com — /content/dam/en-zz/Solutions/Data-Center/a100/pdf/a100-80gb-datasheet-update-nvi", "u": "https://www.nvidia.com/content/dam/en-zz/Solutions/Data-Center/a100/pdf/a100-80gb-datasheet-update-nvidia-us-1521051-r2-web.pdf" }, { "t": "nvidia.com — /content/dam/en-zz/Solutions/Data-Center/a100/pdf/A100-PCIE-Prduct-Brief.pdf", "u": "https://www.nvidia.com/content/dam/en-zz/Solutions/Data-Center/a100/pdf/A100-PCIE-Prduct-Brief.pdf" }, { "t": "images.nvidia.com — /aem-dam/en-zz/Solutions/data-center/nvidia-ampere-architecture-whitepaper.pdf", "u": "https://images.nvidia.com/aem-dam/en-zz/Solutions/data-center/nvidia-ampere-architecture-whitepaper.pdf" } ], "aka": "A100 PCIe 40GB NVIDIA A100 for PCIe" }, { "id": "a100-sxm4-40gb", "name": "NVIDIA A100 40GB SXM", "short": "A100 40GB SXM", "seg": "datacenter", "arch": "Ampere", "archGroup": "Ampere", "cls": "ampere-ga100", "clsLabel": "Ampere GA100 (A100, A30)", "chip": "GA100", "date": "2020-05", "t": 2020.3333333333333, "status": null, "ff": "SXM4 module (HGX A100 4/8-GPU boards; NVLink 600 GB/s)", "mem": 40.0, "memType": "HBM2", "bw": 1555.0, "tdp": 400.0, "sms": 108.0, "tc": 432.0, "cuda": 6912.0, "boost": 1410.0, "v": { "fp32": [ 19.5, null, "p" ], "fp64": [ 9.7, null, "p" ], "fp64tc": [ 19.5, null, "p" ], "tf32": [ 156.0, 312.0, "p" ], "fp16": [ 312.0, 624.0, "p" ], "bf16": [ 312.0, 624.0, "p" ], "int8": [ 624.0, 1248.0, "p" ], "int4": [ 1248.0, 2496.0, "p" ] }, "how": { "fp32": "NVIDIA: “FP32: 19.5 TFLOPS” [nvidia.com]", "fp64": "NVIDIA: “FP64: 9.7 TFLOPS” [nvidia.com]", "fp64tc": "NVIDIA: “FP64 Tensor Core: 19.5 TFLOPS” [nvidia.com]", "tf32": "NVIDIA: “Tensor Float 32 (TF32): 156 TFLOPS | 312 TFLOPS*” [nvidia.com]", "fp16": "NVIDIA: “Peak FP16 Tensor TFLOPS with FP32 Accumulate¹: 312/624³” [images.nvidia.com]", "bf16": "NVIDIA: “BFLOAT16 Tensor Core: 312 TFLOPS | 624 TFLOPS*” [nvidia.com]", "int8": "NVIDIA: “INT8 Tensor Core: 624 TOPS | 1248 TOPS*” [nvidia.com]", "int4": "NVIDIA: “Peak INT4 Tensor Core¹: 1,248 TOPS | 2,496 TOPS²” [images.nvidia.com]" }, "na": { "fp8": "No FP8 tensor cores before Ada/Hopper (FP8 models run at FP16 speed)", "fp6": "No FP6 tensor cores before Blackwell", "fp4": "No FP4 tensor cores before Blackwell" }, "headline": null, "anchor": "Derived from NVIDIA's published FP16 figure of 312 dense. ", "notes": "The GA100 whitepaper describes this SKU (SXM4, 40 GB, 400 W, 1410 MHz). Its Table 4 splits FP16 Tensor into FP16-accumulate and FP32-accumulate (both 312/624); the datasheet gives an unsplit 'FP16 Tensor Core' with the same value. Rates with no schema key (whitepaper Tables 1, 2 and 4): non-tensor FP16 78 TFLOPS, non-tensor BF16 39 TFLOPS, INT32 19.5 TOPS, Binary Tensor Core 4992 TOPS dense (no sparse figure). Whitepaper footnote: 'Peak rates are based on GPU Boost Clock.' The Jun20 datasheet gave bandwidth as '1.6 TB/sec' (rounded).", "sources": [ { "t": "nvidia.com — /content/dam/en-zz/Solutions/Data-Center/a100/pdf/nvidia-a100-datasheet-us-nvidi", "u": "https://www.nvidia.com/content/dam/en-zz/Solutions/Data-Center/a100/pdf/nvidia-a100-datasheet-us-nvidia-1758950-r4-web.pdf" }, { "t": "nvidia.com — /content/dam/en-zz/Solutions/Data-Center/a100/pdf/nvidia-a100-datasheet.pdf", "u": "https://www.nvidia.com/content/dam/en-zz/Solutions/Data-Center/a100/pdf/nvidia-a100-datasheet.pdf" }, { "t": "nvidia.com — /content/dam/en-zz/Solutions/Data-Center/a100/pdf/a100-80gb-datasheet-update-nvi", "u": "https://www.nvidia.com/content/dam/en-zz/Solutions/Data-Center/a100/pdf/a100-80gb-datasheet-update-nvidia-us-1521051-r2-web.pdf" }, { "t": "images.nvidia.com — /aem-dam/en-zz/Solutions/data-center/nvidia-ampere-architecture-whitepaper.pdf", "u": "https://images.nvidia.com/aem-dam/en-zz/Solutions/data-center/nvidia-ampere-architecture-whitepaper.pdf" } ], "aka": "A100 SXM4 40GB NVIDIA A100 for NVIDIA HGX NVIDIA A100 for NVLink" }, { "id": "v100s-pcie-32gb", "name": "NVIDIA V100S PCIe", "short": "V100S PCIe", "seg": "datacenter", "arch": "Volta", "archGroup": "Volta", "cls": "volta", "clsLabel": "Volta (GV100)", "chip": "GV100", "date": "2020-01", "t": 2020.0, "status": null, "ff": "PCIe Gen3, full-height full-length, passive", "mem": 32.0, "memType": "HBM2", "bw": 1134.0, "tdp": 250.0, "sms": 80.0, "tc": 640.0, "cuda": 5120.0, "boost": 1597.0, "v": { "fp32": [ 16.4, null, "p" ], "fp64": [ 8.2, null, "p" ], "fp16": [ 130.0, null, "p" ] }, "how": { "fp32": "NVIDIA: “Single-Precision Performance: 16.4 TFLOPS” [images.nvidia.com]", "fp64": "NVIDIA: “Double-Precision Performance: 8.2 TFLOPS” [images.nvidia.com]", "fp16": "NVIDIA: “Tensor Performance: 130 TFLOPS” (precision not stated; Volta headline figures are FP16) [images.nvidia.com]" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "tf32": "TF32 tensor cores arrived with Ampere", "bf16": "BF16 tensor cores arrived with Ampere", "fp8": "No FP8 tensor cores before Ada/Hopper (FP8 models run at FP16 speed)", "fp6": "No FP6 tensor cores before Blackwell", "fp4": "No FP4 tensor cores before Blackwell", "int8": "No INT8 tensor cores on this architecture", "int4": "No INT4 tensor cores on this architecture" }, "headline": "“Tensor Performance: 130 TFLOPS”", "anchor": "Derived from NVIDIA's headline figure, 130 TFLOPS FP16. ", "notes": "The only NVIDIA spec source is the Jan20 V100/V100S datasheet (r5) plus the regional product page. The prose of that datasheet says 'Equipped with 640 Tensor Cores, V100 delivers 130 teraFLOPS (TFLOPS) of deep learning performance'; that is the V100S figure, while the same sheet's table gives 125 for V100 SXM2 and 112 for V100 PCIe. No NVIDIA launch announcement for V100S was located; the datasheet is dated Jan20.", "sources": [ { "t": "images.nvidia.com — /content/technologies/volta/pdf/volta-v100-datasheet-update-us-1165301-r5.pdf", "u": "https://images.nvidia.com/content/technologies/volta/pdf/volta-v100-datasheet-update-us-1165301-r5.pdf" }, { "t": "nvidia.com — /en-au/data-center/v100/", "u": "https://www.nvidia.com/en-au/data-center/v100/" }, { "t": "images.nvidia.com — /content/volta-architecture/pdf/volta-architecture-whitepaper.pdf", "u": "https://images.nvidia.com/content/volta-architecture/pdf/volta-architecture-whitepaper.pdf" }, { "t": "techpowerup.com — /gpu-specs/tesla-v100s-pcie-32-gb.c3467", "u": "https://www.techpowerup.com/gpu-specs/tesla-v100s-pcie-32-gb.c3467" } ], "aka": "V100S for PCIe Tesla V100S PCIe 32GB" }, { "id": "t4", "name": "NVIDIA T4", "short": "T4", "seg": "datacenter", "arch": "Turing", "archGroup": "Turing", "cls": "turing-pro", "clsLabel": "Turing (Quadro, Tesla, TITAN)", "chip": "TU104", "date": "2018-09", "t": 2018.6666666666667, "status": null, "ff": "Low-profile single-slot PCIe Gen3 x16 card (6.6 in), passive", "mem": 16.0, "memType": "GDDR6", "bw": 320.0, "tdp": 70.0, "sms": 40.0, "tc": 320.0, "cuda": 2560.0, "boost": 1590.0, "v": { "fp32": [ 8.1, null, "p" ], "fp64": [ 0.2531, null, "d" ], "fp16": [ 65.0, null, "p" ], "int8": [ 130.0, null, "p" ], "int4": [ 260.0, null, "p" ] }, "how": { "fp32": "NVIDIA: “Single-Precision: 8.1 TFLOPS” [nvidia.com]", "fp64": "Derived: FP32 ÷ 32 (this architecture's FP64 rate)", "fp16": "NVIDIA: “Peak FP16 Tensor TFLOPS with FP32 Accumulate*: 65” [images.nvidia.com]", "int8": "NVIDIA: “INT8: 130 TOPS” [nvidia.com]", "int4": "NVIDIA: “INT4: 260 TOPS” [nvidia.com]" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "tf32": "TF32 tensor cores arrived with Ampere", "bf16": "BF16 tensor cores arrived with Ampere", "fp8": "No FP8 tensor cores before Ada/Hopper (FP8 models run at FP16 speed)", "fp6": "No FP6 tensor cores before Blackwell", "fp4": "No FP4 tensor cores before Blackwell" }, "headline": null, "anchor": "Derived from NVIDIA's published FP16 figure of 65 dense. ", "notes": "Turing has no structured-sparsity mode, so sparse is null throughout. The datasheet's 'Mixed-Precision (FP16/FP32) 65 TFLOPS' is corroborated by whitepaper Table 5, which lists FP16 Tensor with FP16 accumulate and with FP32 accumulate both at 65 (full rate for T4). No FP64 figure is published. Non-tensor rates without a schema key (Table 5): Peak FP16 16.2 TFLOPS, Peak INT32 8.1 TIPS. Whitepaper note: the 585 MHz base clock is 'the lowest clock that would typically be seen in very stressful inferencing workloads'; peak rates are at boost. CONFLICT: memory bandwidth is 300 GB/sec in the datasheet, 320 in the product brief and whitepaper, and '320+' on the product page.", "sources": [ { "t": "nvidia.com — /content/dam/en-zz/Solutions/Data-Center/tesla-t4/t4-tensor-core-datasheet-95164", "u": "https://www.nvidia.com/content/dam/en-zz/Solutions/Data-Center/tesla-t4/t4-tensor-core-datasheet-951643.pdf" }, { "t": "nvidia.com — /content/dam/en-zz/Solutions/Data-Center/tesla-t4/t4-tensor-core-product-brief.p", "u": "https://www.nvidia.com/content/dam/en-zz/Solutions/Data-Center/tesla-t4/t4-tensor-core-product-brief.pdf" }, { "t": "images.nvidia.com — /aem-dam/en-zz/Solutions/design-visualization/technologies/turing-architecture/N", "u": "https://images.nvidia.com/aem-dam/en-zz/Solutions/design-visualization/technologies/turing-architecture/NVIDIA-Turing-Architecture-Whitepaper.pdf" }, { "t": "nvidia.com — /en-us/data-center/tesla-t4/", "u": "https://www.nvidia.com/en-us/data-center/tesla-t4/" } ], "aka": "Tesla T4 NVIDIA T4 Tensor Core GPU" }, { "id": "v100-pcie-32gb", "name": "Tesla V100 PCIe 32GB", "short": "Tesla V100 PCIe 32GB", "seg": "datacenter", "arch": "Volta", "archGroup": "Volta", "cls": "volta", "clsLabel": "Volta (GV100)", "chip": "GV100", "date": "2018-03", "t": 2018.1666666666667, "status": null, "ff": "PCIe Gen3 x16, full-height full-length dual-slot 10.5 in, passive", "mem": 32.0, "memType": "HBM2", "bw": 900.0, "tdp": 250.0, "sms": 80.0, "tc": 640.0, "cuda": 5120.0, "boost": 1380.0, "v": { "fp32": [ 14.0, null, "p" ], "fp64": [ 7.0, null, "p" ], "fp16": [ 112.0, null, "p" ] }, "how": { "fp32": "NVIDIA: “Single-Precision Performance: 14 TFLOPS” [images.nvidia.com]", "fp64": "NVIDIA: “Double-Precision Performance: 7 TFLOPS” [images.nvidia.com]", "fp16": "NVIDIA: “Tensor Performance: 112 TFLOPS” (precision not stated; Volta headline figures are FP16) [images.nvidia.com]" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "tf32": "TF32 tensor cores arrived with Ampere", "bf16": "BF16 tensor cores arrived with Ampere", "fp8": "No FP8 tensor cores before Ada/Hopper (FP8 models run at FP16 speed)", "fp6": "No FP6 tensor cores before Blackwell", "fp4": "No FP4 tensor cores before Blackwell", "int8": "No INT8 tensor cores on this architecture", "int4": "No INT4 tensor cores on this architecture" }, "headline": "“Tensor Performance: 112 TFLOPS”", "anchor": "Derived from NVIDIA's headline figure, 112 TFLOPS FP16. ", "notes": "Product brief PB-08744-001_v05 (Mar 2018) added the 32GB SKU. Its base clock is 1230 MHz (16GB: 1245 MHz); max boost is the same 1380 MHz. The datasheets publish one PCIe column covering 32GB and 16GB, so peaks equal the 16GB card's. 'Tensor Performance' is unqualified, so it is recorded as headline_tensor.", "sources": [ { "t": "images.nvidia.com — /content/technologies/volta/pdf/volta-v100-datasheet-update-us-1165301-r5.pdf", "u": "https://images.nvidia.com/content/technologies/volta/pdf/volta-v100-datasheet-update-us-1165301-r5.pdf" }, { "t": "images.nvidia.com — /content/technologies/volta/pdf/tesla-volta-v100-datasheet-letter-fnl-web.pdf", "u": "https://images.nvidia.com/content/technologies/volta/pdf/tesla-volta-v100-datasheet-letter-fnl-web.pdf" }, { "t": "images.nvidia.com — /content/tesla/pdf/Tesla-V100-PCIe-Product-Brief.pdf", "u": "https://images.nvidia.com/content/tesla/pdf/Tesla-V100-PCIe-Product-Brief.pdf" }, { "t": "images.nvidia.com — /content/volta-architecture/pdf/volta-architecture-whitepaper.pdf", "u": "https://images.nvidia.com/content/volta-architecture/pdf/volta-architecture-whitepaper.pdf" }, { "t": "nvidia.com — /en-au/data-center/v100/", "u": "https://www.nvidia.com/en-au/data-center/v100/" } ], "aka": "NVIDIA V100 PCIe V100 for PCIe" }, { "id": "v100-sxm2-32gb", "name": "Tesla V100 SXM2 32GB", "short": "Tesla V100 SXM2 32GB", "seg": "datacenter", "arch": "Volta", "archGroup": "Volta", "cls": "volta", "clsLabel": "Volta (GV100)", "chip": "GV100", "date": "2018-03", "t": 2018.1666666666667, "status": null, "ff": "SXM2 module (NVLink 300 GB/s)", "mem": 32.0, "memType": "HBM2", "bw": 900.0, "tdp": 300.0, "sms": 80.0, "tc": 640.0, "cuda": 5120.0, "boost": 1530.0, "v": { "fp32": [ 15.7, null, "p" ], "fp64": [ 7.8, null, "p" ], "fp16": [ 125.0, null, "p" ] }, "how": { "fp32": "NVIDIA: “Single-Precision Performance: 15.7 TFLOPS” [images.nvidia.com]", "fp64": "NVIDIA: “Double-Precision Performance: 7.8 TFLOPS” [images.nvidia.com]", "fp16": "NVIDIA: “Peak FP16 Tensor TFLOPS with FP32 Accumulate¹: 125” [images.nvidia.com]" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "tf32": "TF32 tensor cores arrived with Ampere", "bf16": "BF16 tensor cores arrived with Ampere", "fp8": "No FP8 tensor cores before Ada/Hopper (FP8 models run at FP16 speed)", "fp6": "No FP6 tensor cores before Blackwell", "fp4": "No FP4 tensor cores before Blackwell", "int8": "No INT8 tensor cores on this architecture", "int4": "No INT4 tensor cores on this architecture" }, "headline": "“Tensor Performance: 125 TFLOPS”", "anchor": "Derived from NVIDIA's published FP16 figure of 125 dense. ", "notes": "The datasheets publish one SXM2 column covering 32GB and 16GB, so the numbers match the 16GB card. Boost clock comes from GA100 whitepaper Table 4, whose V100 column is 'SXM2' with Memory Size '32 GB / 16 GB'. Not covered: the V100 SXM3-32GB used in DGX-2/HGX-2, which appears only in a benchmark footnote of the Jan20 datasheet, with no spec column.", "sources": [ { "t": "images.nvidia.com — /content/technologies/volta/pdf/volta-v100-datasheet-update-us-1165301-r5.pdf", "u": "https://images.nvidia.com/content/technologies/volta/pdf/volta-v100-datasheet-update-us-1165301-r5.pdf" }, { "t": "images.nvidia.com — /content/technologies/volta/pdf/tesla-volta-v100-datasheet-letter-fnl-web.pdf", "u": "https://images.nvidia.com/content/technologies/volta/pdf/tesla-volta-v100-datasheet-letter-fnl-web.pdf" }, { "t": "images.nvidia.com — /aem-dam/en-zz/Solutions/data-center/nvidia-ampere-architecture-whitepaper.pdf", "u": "https://images.nvidia.com/aem-dam/en-zz/Solutions/data-center/nvidia-ampere-architecture-whitepaper.pdf" }, { "t": "images.nvidia.com — /content/volta-architecture/pdf/volta-architecture-whitepaper.pdf", "u": "https://images.nvidia.com/content/volta-architecture/pdf/volta-architecture-whitepaper.pdf" }, { "t": "nvidia.com — /en-au/data-center/v100/", "u": "https://www.nvidia.com/en-au/data-center/v100/" } ], "aka": "NVIDIA V100 SXM2 V100 for NVLink" }, { "id": "v100-pcie-16gb", "name": "Tesla V100 PCIe 16GB", "short": "Tesla V100 PCIe 16GB", "seg": "datacenter", "arch": "Volta", "archGroup": "Volta", "cls": "volta", "clsLabel": "Volta (GV100)", "chip": "GV100", "date": "2017-06", "t": 2017.4166666666667, "status": null, "ff": "PCIe Gen3 x16, full-height full-length dual-slot 10.5 in, passive", "mem": 16.0, "memType": "HBM2", "bw": 900.0, "tdp": 250.0, "sms": 80.0, "tc": 640.0, "cuda": 5120.0, "boost": 1380.0, "v": { "fp32": [ 14.0, null, "p" ], "fp64": [ 7.0, null, "p" ], "fp16": [ 112.0, null, "p" ] }, "how": { "fp32": "NVIDIA: “Single-Precision Performance: 14 TFLOPS” [images.nvidia.com]", "fp64": "NVIDIA: “Double-Precision Performance: 7 TFLOPS” [images.nvidia.com]", "fp16": "NVIDIA: “Tensor Performance: 112 TFLOPS” (precision not stated; Volta headline figures are FP16) [images.nvidia.com]" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "tf32": "TF32 tensor cores arrived with Ampere", "bf16": "BF16 tensor cores arrived with Ampere", "fp8": "No FP8 tensor cores before Ada/Hopper (FP8 models run at FP16 speed)", "fp6": "No FP6 tensor cores before Blackwell", "fp4": "No FP4 tensor cores before Blackwell", "int8": "No INT8 tensor cores on this architecture", "int4": "No INT4 tensor cores on this architecture" }, "headline": "“Tensor Performance: 112 TFLOPS”", "anchor": "Derived from NVIDIA's headline figure, 112 TFLOPS FP16. ", "notes": "PCIe peaks are identical in all three NVIDIA datasheets (Jul17, Mar18, Jan20): 7 / 14 / 112. The datasheets cover the 16GB and 32GB PCIe cards in one column. 'Tensor Performance' is unqualified, so it is recorded as headline_tensor. The Volta whitepaper says Volta Tensor Cores take FP16 inputs and accumulate in FP16 or FP32, but NVIDIA publishes no per-accumulate split for the PCIe card. The product page header reads 'PERFORMANCE with NVIDIA GPU Boost'. The en-us V100 product page now redirects to the generic data-center page; the en-au page still has the spec table.", "sources": [ { "t": "images.nvidia.com — /content/technologies/volta/pdf/volta-v100-datasheet-update-us-1165301-r5.pdf", "u": "https://images.nvidia.com/content/technologies/volta/pdf/volta-v100-datasheet-update-us-1165301-r5.pdf" }, { "t": "images.nvidia.com — /content/technologies/volta/pdf/tesla-volta-v100-datasheet-letter-fnl-web.pdf", "u": "https://images.nvidia.com/content/technologies/volta/pdf/tesla-volta-v100-datasheet-letter-fnl-web.pdf" }, { "t": "images.nvidia.com — /content/technologies/volta/pdf/437317-Volta-V100-DS-NV-US-WEB.pdf", "u": "https://images.nvidia.com/content/technologies/volta/pdf/437317-Volta-V100-DS-NV-US-WEB.pdf" }, { "t": "images.nvidia.com — /content/tesla/pdf/Tesla-V100-PCIe-Product-Brief.pdf", "u": "https://images.nvidia.com/content/tesla/pdf/Tesla-V100-PCIe-Product-Brief.pdf" }, { "t": "nvidia.com — /content/dam/en-zz/Solutions/Data-Center/tesla-product-literature/Tesla-V100-PCI", "u": "https://www.nvidia.com/content/dam/en-zz/Solutions/Data-Center/tesla-product-literature/Tesla-V100-PCIe-Product-Brief.pdf" }, { "t": "images.nvidia.com — /content/volta-architecture/pdf/volta-architecture-whitepaper.pdf", "u": "https://images.nvidia.com/content/volta-architecture/pdf/volta-architecture-whitepaper.pdf" }, { "t": "nvidia.com — /en-au/data-center/v100/", "u": "https://www.nvidia.com/en-au/data-center/v100/" } ], "aka": "NVIDIA V100 PCIe V100 for PCIe" }, { "id": "v100-sxm2-16gb", "name": "Tesla V100 SXM2 16GB", "short": "Tesla V100 SXM2 16GB", "seg": "datacenter", "arch": "Volta", "archGroup": "Volta", "cls": "volta", "clsLabel": "Volta (GV100)", "chip": "GV100", "date": "2017-05", "t": 2017.3333333333333, "status": null, "ff": "SXM2 module (NVLink 300 GB/s)", "mem": 16.0, "memType": "HBM2", "bw": 900.0, "tdp": 300.0, "sms": 80.0, "tc": 640.0, "cuda": 5120.0, "boost": 1530.0, "v": { "fp32": [ 15.7, null, "p" ], "fp64": [ 7.8, null, "p" ], "fp16": [ 125.0, null, "p" ] }, "how": { "fp32": "NVIDIA: “Single-Precision Performance: 15.7 TFLOPS” [images.nvidia.com]", "fp64": "NVIDIA: “Double-Precision Performance: 7.8 TFLOPS” [images.nvidia.com]", "fp16": "NVIDIA: “Peak FP16 Tensor TFLOPS with FP32 Accumulate¹: 125” [images.nvidia.com]" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "tf32": "TF32 tensor cores arrived with Ampere", "bf16": "BF16 tensor cores arrived with Ampere", "fp8": "No FP8 tensor cores before Ada/Hopper (FP8 models run at FP16 speed)", "fp6": "No FP6 tensor cores before Blackwell", "fp4": "No FP4 tensor cores before Blackwell", "int8": "No INT8 tensor cores on this architecture", "int4": "No INT4 tensor cores on this architecture" }, "headline": "“Tensor Performance: 125 TFLOPS”", "anchor": "Derived from NVIDIA's published FP16 figure of 125 dense. ", "notes": "CONFLICT (superseded figure): the first datasheet (Jul17, 437317) lists SXM2 at 7.5 TFLOPS FP64 / 15 TFLOPS FP32 / 120 TFLOPS Tensor, and its prose says '120 TeraFLOPS of deep learning performance'. Its benchmark footnotes say V100 was 'measured on pre-production hardware'. The Mar18 and Jan20 datasheets and the Volta whitepaper give 7.8 / 15.7 / 125, which are the values recorded here. The GA100 whitepaper Table 4 (V100 column: SXM2, 32 GB / 16 GB, 1530 MHz) gives the FP16-accumulate and FP32-accumulate splits (both 125). Non-tensor rates published there without a schema key: FP16 31.4 TFLOPS, INT32 15.7 TOPS. GA100 whitepaper Table 2 also gives non-tensor 'V100 INT8' at 62 TOPS. All peak rates are at GPU Boost clock (whitepaper footnote).", "sources": [ { "t": "images.nvidia.com — /content/technologies/volta/pdf/volta-v100-datasheet-update-us-1165301-r5.pdf", "u": "https://images.nvidia.com/content/technologies/volta/pdf/volta-v100-datasheet-update-us-1165301-r5.pdf" }, { "t": "images.nvidia.com — /content/technologies/volta/pdf/tesla-volta-v100-datasheet-letter-fnl-web.pdf", "u": "https://images.nvidia.com/content/technologies/volta/pdf/tesla-volta-v100-datasheet-letter-fnl-web.pdf" }, { "t": "images.nvidia.com — /content/technologies/volta/pdf/437317-Volta-V100-DS-NV-US-WEB.pdf", "u": "https://images.nvidia.com/content/technologies/volta/pdf/437317-Volta-V100-DS-NV-US-WEB.pdf" }, { "t": "images.nvidia.com — /content/volta-architecture/pdf/volta-architecture-whitepaper.pdf", "u": "https://images.nvidia.com/content/volta-architecture/pdf/volta-architecture-whitepaper.pdf" }, { "t": "images.nvidia.com — /aem-dam/en-zz/Solutions/data-center/nvidia-ampere-architecture-whitepaper.pdf", "u": "https://images.nvidia.com/aem-dam/en-zz/Solutions/data-center/nvidia-ampere-architecture-whitepaper.pdf" }, { "t": "nvidia.com — /en-au/data-center/v100/", "u": "https://www.nvidia.com/en-au/data-center/v100/" } ], "aka": "NVIDIA V100 SXM2 V100 for NVLink" }, { "id": "rtx-pro-4500-blackwell-server", "name": "NVIDIA RTX PRO 4500 Blackwell Server Edition", "short": "RTX PRO 4500 Server", "seg": "datacenter", "arch": "Blackwell", "archGroup": "Blackwell", "cls": "blackwell-pro", "clsLabel": "Blackwell GB20x (RTX PRO)", "chip": "GB203", "date": null, "t": null, "status": null, "ff": "PCIe 5.0 x16, single-slot FHFL (4.4 in x 10.5 in), passive", "mem": 32.0, "memType": "GDDR7", "bw": 800.0, "tdp": 165.0, "sms": null, "tc": null, "cuda": 10496.0, "boost": null, "v": { "fp32": [ 51.0, null, "p" ], "fp64": [ 0.7969, null, "d" ], "tf32": [ 101.5, 203.0, "p" ], "fp16": [ 203.0, 406.0, "p" ], "bf16": [ 203.0, 406.0, "p" ], "fp8": [ 405.5, 811.0, "p" ], "fp4": [ 800.0, 1600.0, "p" ], "int8": [ 406.0, 812.0, "d" ] }, "how": { "fp32": "NVIDIA: “Tensor Single-Precision Performance (FP32) 51 TFLOPS (label as printed)” [dam-cdn.nvd.orangelogic.com]", "fp64": "Derived: FP32 ÷ 64 (this architecture's FP64 rate)", "tf32": "NVIDIA: “TF32 Tensor Core 203 TFLOPS (read as sparse; see notes)” (dense = half the published sparse figure) [dam-cdn.nvd.orangelogic.com]", "fp16": "NVIDIA: “FP16 | BF16 Tensor Core 406 TFLOPS (read as sparse; see notes)” (dense = half the published sparse figure) [dam-cdn.nvd.orangelogic.com]", "bf16": "NVIDIA: “FP16 | BF16 Tensor Core 406 TFLOPS (read as sparse; see notes)” (dense = half the published sparse figure) [dam-cdn.nvd.orangelogic.com]", "fp8": "NVIDIA: “FP8 Tensor Core 811 TFLOPS (read as sparse; see notes)” (dense = half the published sparse figure) [dam-cdn.nvd.orangelogic.com]", "fp4": "NVIDIA: “FP4 Tensor Core 1.6 PFLOPS (read as sparse; see notes)” (dense = half the published sparse figure) [dam-cdn.nvd.orangelogic.com]", "int8": "Derived from NVIDIA's published FP16 figure of 203 dense. On RTX PRO Blackwell, INT8 runs at twice the FP16 rate" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "fp6": "RTX Blackwell supports FP6, but NVIDIA publishes no FP6 rate for it", "int4": "NVIDIA lists no INT4 rate for Blackwell" }, "headline": null, "anchor": "Derived from NVIDIA's published FP16 figure of 203 dense. ", "notes": "NVIDIA's datasheet gives no dense/sparse labels. Every tensor figure matches the sparse rate of 82 SMs (one per RT core) at the clock its 51 TFLOPS FP32 implies, so they are read as sparse.", "sources": [ { "t": "dam-cdn.nvd.orangelogic.com — /AssetLink/x4x3l8i437r0s53bi55omn7y4o2bda4m.pdf", "u": "https://dam-cdn.nvd.orangelogic.com/AssetLink/x4x3l8i437r0s53bi55omn7y4o2bda4m.pdf" }, { "t": "nvidia.com — /en-us/data-center/rtx-pro-4500-blackwell-server-edition/", "u": "https://www.nvidia.com/en-us/data-center/rtx-pro-4500-blackwell-server-edition/" } ], "aka": null }, { "id": "rtx-pro-5000-72gb-blackwell", "name": "NVIDIA RTX PRO 5000 Blackwell 72GB", "short": "RTX PRO 5000 Blackwell 72GB", "seg": "workstation", "arch": "Blackwell", "archGroup": "Blackwell", "cls": "blackwell-pro", "clsLabel": "Blackwell GB20x (RTX PRO)", "chip": "GB202", "date": "2025-12", "t": 2025.9166666666667, "status": null, "ff": "4.4\" x 10.5\" L, dual slot, full height", "mem": 72.0, "memType": "GDDR7", "bw": 1344.0, "tdp": 300.0, "sms": null, "tc": 440.0, "cuda": 14080.0, "boost": null, "v": { "fp32": [ 65.0, null, "p" ], "fp64": [ 1.0156, null, "d" ], "tf32": [ 129.0, 258.0, "d" ], "fp16": [ 258.0, 516.0, "d" ], "bf16": [ 258.0, 516.0, "d" ], "fp8": [ 516.0, 1032.0, "d" ], "fp4": [ 1032.0, 2064.0, "p" ], "int8": [ 516.0, 1032.0, "d" ] }, "how": { "fp32": "NVIDIA: “Single-Precision Performance 65 TFLOPS1 | 1. Peak rates based on GPU Boost Clock.” [nvidia.com]", "fp64": "Derived: FP32 ÷ 64 (this architecture's FP64 rate)", "tf32": "Derived from NVIDIA's published FP4 figure of 1,032 dense. On RTX PRO Blackwell, TF32 runs at an eighth of the FP4 rate", "fp16": "Derived from NVIDIA's published FP4 figure of 1,032 dense. On RTX PRO Blackwell, FP16 runs at a quarter of the FP4 rate", "bf16": "Derived from NVIDIA's published FP4 figure of 1,032 dense. On RTX PRO Blackwell, BF16 runs at a quarter of the FP4 rate", "fp8": "Derived from NVIDIA's published FP4 figure of 1,032 dense. On RTX PRO Blackwell, FP8 runs at half the FP4 rate", "fp4": "NVIDIA: “AI TOPS 2,064 AI TOPS1,2 | 2. Effective FP4 TOPS with sparsity.” (dense = half the published sparse figure) [nvidia.com]", "int8": "Derived from NVIDIA's published FP4 figure of 1,032 dense. On RTX PRO Blackwell, INT8 runs at half the FP4 rate" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "fp6": "RTX Blackwell supports FP6, but NVIDIA publishes no FP6 rate for it", "int4": "NVIDIA lists no INT4 rate for Blackwell" }, "headline": "“AI TOPS 2,064 AI TOPS1,2 (merged 48GB/72GB column) | 1. Peak rates based on GPU Boost Clock. 2. Effective FP4 TOPS with sparsity.” — read as FP4, sparse", "anchor": "Derived from NVIDIA's published FP4 figure of 1,032 dense. ", "notes": "CONFLICT: NVIDIA blog (2025-12-18) says 2,142 TOPS for the 72GB model; datasheet and product page give a single 2,064 AI TOPS figure covering both 48GB and 72GB.; MIG up to 2x 36 GB / 1x 72 GB (datasheet). Boost clock not published by NVIDIA.", "sources": [ { "t": "nvidia.com — /content/dam/en-zz/Solutions/products/workstations/professional-desktop-gpus/rtx", "u": "https://www.nvidia.com/content/dam/en-zz/Solutions/products/workstations/professional-desktop-gpus/rtx-pro-5000-blackwell/workstation-datasheet-blackwell-rtx-pro-5000-5488550-nvidia.pdf" }, { "t": "nvidia.com — /en-us/products/workstations/professional-desktop-gpus/rtx-pro-5000/", "u": "https://www.nvidia.com/en-us/products/workstations/professional-desktop-gpus/rtx-pro-5000/" }, { "t": "blogs.nvidia.com — /blog/rtx-pro-5000-72gb-blackwell-gpu/", "u": "https://blogs.nvidia.com/blog/rtx-pro-5000-72gb-blackwell-gpu/" }, { "t": "pny.com — /nvidia-rtx-pro-5000-72gb-blackwell", "u": "https://www.pny.com/nvidia-rtx-pro-5000-72gb-blackwell" } ], "aka": null }, { "id": "rtx-pro-2000-blackwell", "name": "NVIDIA RTX PRO 2000 Blackwell", "short": "RTX PRO 2000 Blackwell", "seg": "workstation", "arch": "Blackwell", "archGroup": "Blackwell", "cls": "blackwell-pro", "clsLabel": "Blackwell GB20x (RTX PRO)", "chip": "GB206", "date": "2025-08", "t": 2025.5833333333333, "status": null, "ff": "2.7\" H x 6.6\" L, dual slot", "mem": 16.0, "memType": "GDDR7", "bw": 288.0, "tdp": 70.0, "sms": null, "tc": 136.0, "cuda": 4352.0, "boost": null, "v": { "fp32": [ 17.0, null, "p" ], "fp64": [ 0.2656, null, "d" ], "tf32": [ 34.0625, 68.125, "d" ], "fp16": [ 68.125, 136.25, "d" ], "bf16": [ 68.125, 136.25, "d" ], "fp8": [ 136.25, 272.5, "d" ], "fp4": [ 272.5, 545.0, "p" ], "int8": [ 136.25, 272.5, "d" ] }, "how": { "fp32": "NVIDIA: “Single-Precision Performance 17 TFLOPS1 | 1. Peak rates based on GPU Boost Clock.” [nvidia.com]", "fp64": "Derived: FP32 ÷ 64 (this architecture's FP64 rate)", "tf32": "Derived from NVIDIA's published FP4 figure of 272.5 dense. On RTX PRO Blackwell, TF32 runs at an eighth of the FP4 rate", "fp16": "Derived from NVIDIA's published FP4 figure of 272.5 dense. On RTX PRO Blackwell, FP16 runs at a quarter of the FP4 rate", "bf16": "Derived from NVIDIA's published FP4 figure of 272.5 dense. On RTX PRO Blackwell, BF16 runs at a quarter of the FP4 rate", "fp8": "Derived from NVIDIA's published FP4 figure of 272.5 dense. On RTX PRO Blackwell, FP8 runs at half the FP4 rate", "fp4": "NVIDIA: “AI TOPS 545 AI TOPS1,2 | 2. Effective FP4 TOPS with sparsity.” (dense = half the published sparse figure) [nvidia.com]", "int8": "Derived from NVIDIA's published FP4 figure of 272.5 dense. On RTX PRO Blackwell, INT8 runs at half the FP4 rate" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "fp6": "RTX Blackwell supports FP6, but NVIDIA publishes no FP6 rate for it", "int4": "NVIDIA lists no INT4 rate for Blackwell" }, "headline": "“AI TOPS 545 AI TOPS1,2 | 1. Peak rates based on GPU Boost Clock. 2. Effective FP4 TOPS with sparsity.” — read as FP4, sparse", "anchor": "Derived from NVIDIA's published FP4 figure of 272.5 dense. ", "notes": "Datasheet revision Jun26 (doc 5322351); product page spec table shows 'AI TOPS 545'.; Boost clock and SM count not published by NVIDIA; TechPowerUp entry not located.", "sources": [ { "t": "nvidia.com — /content/dam/en-zz/Solutions/products/workstations/professional-desktop-gpus/rtx", "u": "https://www.nvidia.com/content/dam/en-zz/Solutions/products/workstations/professional-desktop-gpus/rtx-pro-2000/workstation-datasheet-blackwell-rtx-pro-2000-nvidia-us-4016661.pdf" }, { "t": "nvidia.com — /en-us/products/workstations/professional-desktop-gpus/rtx-pro-2000/", "u": "https://www.nvidia.com/en-us/products/workstations/professional-desktop-gpus/rtx-pro-2000/" }, { "t": "pny.com — /nvidia-rtx-pro-2000-blackwell", "u": "https://www.pny.com/nvidia-rtx-pro-2000-blackwell" }, { "t": "blogs.nvidia.com — /blog/blackwell-ai-acceleration-workstation-rtx-pro/", "u": "https://blogs.nvidia.com/blog/blackwell-ai-acceleration-workstation-rtx-pro/" } ], "aka": null }, { "id": "rtx-pro-4000-sff-blackwell", "name": "NVIDIA RTX PRO 4000 Blackwell SFF", "short": "RTX PRO 4000 Blackwell SFF", "seg": "workstation", "arch": "Blackwell", "archGroup": "Blackwell", "cls": "blackwell-pro", "clsLabel": "Blackwell GB20x (RTX PRO)", "chip": "GB203", "date": "2025-08", "t": 2025.5833333333333, "status": null, "ff": "2.7\" x 6.6\" L, dual slot, half height", "mem": 24.0, "memType": "GDDR7", "bw": 432.0, "tdp": 70.0, "sms": null, "tc": 280.0, "cuda": 8960.0, "boost": null, "v": { "fp32": [ 24.0, null, "p" ], "fp64": [ 0.375, null, "d" ], "tf32": [ 48.125, 96.25, "d" ], "fp16": [ 96.25, 192.5, "d" ], "bf16": [ 96.25, 192.5, "d" ], "fp8": [ 192.5, 385.0, "d" ], "fp4": [ 385.0, 770.0, "p" ], "int8": [ 192.5, 385.0, "d" ] }, "how": { "fp32": "NVIDIA: “Single-Precision Performance 24 TFLOPS1 | 1. Peak rates based on GPU Boost Clock.” [nvidia.com]", "fp64": "Derived: FP32 ÷ 64 (this architecture's FP64 rate)", "tf32": "Derived from NVIDIA's published FP4 figure of 385 dense. On RTX PRO Blackwell, TF32 runs at an eighth of the FP4 rate", "fp16": "Derived from NVIDIA's published FP4 figure of 385 dense. On RTX PRO Blackwell, FP16 runs at a quarter of the FP4 rate", "bf16": "Derived from NVIDIA's published FP4 figure of 385 dense. On RTX PRO Blackwell, BF16 runs at a quarter of the FP4 rate", "fp8": "Derived from NVIDIA's published FP4 figure of 385 dense. On RTX PRO Blackwell, FP8 runs at half the FP4 rate", "fp4": "NVIDIA: “AI Performance 770 TOPS1,2 | 2. Theoretical FP4 TOPS using sparsity.” (dense = half the published sparse figure) [nvidia.com]", "int8": "Derived from NVIDIA's published FP4 figure of 385 dense. On RTX PRO Blackwell, INT8 runs at half the FP4 rate" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "fp6": "RTX Blackwell supports FP6, but NVIDIA publishes no FP6 rate for it", "int4": "NVIDIA lists no INT4 rate for Blackwell" }, "headline": "“AI TOPS 770 AI TOPS1,2 (datasheet) | product page: '770 TOPS1,2 ... 1. Peak rates based on GPU Boost Clock. I 2. Theoretical FP4 TOPS using sparsity.'” — read as FP4, sparse", "anchor": "Derived from NVIDIA's published FP4 figure of 385 dense. ", "notes": "Aug25 datasheet (doc 4016700) had no throughput rows; Jun26 revision (doc 5322500) adds 770 AI TOPS / 24 TFLOPS / 73 TFLOPS RT but with broken footnote references.; PCIe 5.0 x8 (full-length connector). Boost clock not published by NVIDIA; TechPowerUp entry not located.", "sources": [ { "t": "nvidia.com — /content/dam/en-zz/Solutions/products/workstations/professional-desktop-gpus/rtx", "u": "https://www.nvidia.com/content/dam/en-zz/Solutions/products/workstations/professional-desktop-gpus/rtx-pro-4000-sff/workstation-datasheet-blackwell-rtx-pro-4000-sff-nvidia-us-4016700.pdf" }, { "t": "nvidia.com — /content/dam/en-zz/Solutions/data-center/rtx-pro-4000-blackwell/workstation-data", "u": "https://www.nvidia.com/content/dam/en-zz/Solutions/data-center/rtx-pro-4000-blackwell/workstation-datasheet-blackwell-rtx-pro-4000-gtc25s-nvidia-3662515-r6.pdf" }, { "t": "nvidia.com — /en-us/products/workstations/professional-desktop-gpus/rtx-pro-4000-sff/", "u": "https://www.nvidia.com/en-us/products/workstations/professional-desktop-gpus/rtx-pro-4000-sff/" }, { "t": "pny.com — /nvidia-rtx-pro-4000-sff-blackwell", "u": "https://www.pny.com/nvidia-rtx-pro-4000-sff-blackwell" }, { "t": "blogs.nvidia.com — /blog/blackwell-ai-acceleration-workstation-rtx-pro/", "u": "https://blogs.nvidia.com/blog/blackwell-ai-acceleration-workstation-rtx-pro/" } ], "aka": null }, { "id": "rtx-pro-4000-blackwell", "name": "NVIDIA RTX PRO 4000 Blackwell", "short": "RTX PRO 4000 Blackwell", "seg": "workstation", "arch": "Blackwell", "archGroup": "Blackwell", "cls": "blackwell-pro", "clsLabel": "Blackwell GB20x (RTX PRO)", "chip": "GB203", "date": "2025-03", "t": 2025.1666666666667, "status": null, "ff": "4.4\" x 9.5\" L, single slot, full height", "mem": 24.0, "memType": "GDDR7", "bw": 672.0, "tdp": 145.0, "sms": null, "tc": 280.0, "cuda": 8960.0, "boost": 2055.0, "v": { "fp32": [ 37.0, null, "p" ], "fp64": [ 0.5781, null, "d" ], "tf32": [ 73.625, 147.25, "d" ], "fp16": [ 147.25, 294.5, "d" ], "bf16": [ 147.25, 294.5, "d" ], "fp8": [ 294.5, 589.0, "d" ], "fp4": [ 589.0, 1178.0, "p" ], "int8": [ 294.5, 589.0, "d" ] }, "how": { "fp32": "NVIDIA: “Single-Precision Performance1 37 TFLOPS | 1 Peak rates are based on GPU boost clock.” [nvidia.com]", "fp64": "Derived: FP32 ÷ 64 (this architecture's FP64 rate)", "tf32": "Derived from NVIDIA's published FP4 figure of 589 dense. On RTX PRO Blackwell, TF32 runs at an eighth of the FP4 rate", "fp16": "Derived from NVIDIA's published FP4 figure of 589 dense. On RTX PRO Blackwell, FP16 runs at a quarter of the FP4 rate", "bf16": "Derived from NVIDIA's published FP4 figure of 589 dense. On RTX PRO Blackwell, BF16 runs at a quarter of the FP4 rate", "fp8": "Derived from NVIDIA's published FP4 figure of 589 dense. On RTX PRO Blackwell, FP8 runs at half the FP4 rate", "fp4": "NVIDIA: “AI Performance1 1,178 AI TOPS2 | 2 Theoretical FP4 TOPS using the sparsity feature.” (dense = half the published sparse figure) [nvidia.com]", "int8": "Derived from NVIDIA's published FP4 figure of 589 dense. On RTX PRO Blackwell, INT8 runs at half the FP4 rate" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "fp6": "RTX Blackwell supports FP6, but NVIDIA publishes no FP6 rate for it", "int4": "NVIDIA lists no INT4 rate for Blackwell" }, "headline": "“AI Performance1 1,178 AI TOPS2 | 1 Peak rates are based on GPU boost clock. 2 Theoretical FP4 TOPS using the sparsity feature.” — read as FP4, sparse", "anchor": "Derived from NVIDIA's published FP4 figure of 589 dense. ", "notes": "CONFLICT: datasheet (Sep25 doc 4223416 and Jun26 doc 5323450) says 1,178 AI TOPS / 37 TFLOPS / 112 TFLOPS RT; NVIDIA product page (unchanged since Mar 2025) says 1290 TOPS / 40 TFLOPS / 122 TFLOPS RT. TechPowerUp's 2055 MHz boost matches the datasheet set.; The original GTC25 datasheet URL (...rtx-pro-4000-gtc25s-nvidia-3662515-r6.pdf) now serves the RTX PRO 4000 SFF datasheet.", "sources": [ { "t": "nvidia.com — /content/dam/en-zz/Solutions/products/workstations/professional-desktop-gpus/rtx", "u": "https://www.nvidia.com/content/dam/en-zz/Solutions/products/workstations/professional-desktop-gpus/rtx-pro-4000/workstation-datasheet-rtx-pro-4000-nvidia-us-web.pdf" }, { "t": "web.archive.org — /web/20251209092050/https://www.nvidia.com/content/dam/en-zz/Solutions/products/", "u": "https://web.archive.org/web/20251209092050/https://www.nvidia.com/content/dam/en-zz/Solutions/products/workstations/professional-desktop-gpus/rtx-pro-4000/workstation-datasheet-rtx-pro-4000-nvidia-us-web.pdf" }, { "t": "nvidia.com — /en-us/products/workstations/professional-desktop-gpus/rtx-pro-4000/", "u": "https://www.nvidia.com/en-us/products/workstations/professional-desktop-gpus/rtx-pro-4000/" }, { "t": "web.archive.org — /web/20250324182123/https://www.nvidia.com/en-us/products/workstations/professio", "u": "https://web.archive.org/web/20250324182123/https://www.nvidia.com/en-us/products/workstations/professional-desktop-gpus/rtx-pro-4000/" }, { "t": "pny.com — /nvidia-rtx-pro-4000-blackwell", "u": "https://www.pny.com/nvidia-rtx-pro-4000-blackwell" }, { "t": "techpowerup.com — /gpu-specs/rtx-pro-4000-blackwell.c4279", "u": "https://www.techpowerup.com/gpu-specs/rtx-pro-4000-blackwell.c4279" } ], "aka": null }, { "id": "rtx-pro-4500-blackwell", "name": "NVIDIA RTX PRO 4500 Blackwell", "short": "RTX PRO 4500 Blackwell", "seg": "workstation", "arch": "Blackwell", "archGroup": "Blackwell", "cls": "blackwell-pro", "clsLabel": "Blackwell GB20x (RTX PRO)", "chip": "GB203", "date": "2025-03", "t": 2025.1666666666667, "status": null, "ff": "4.4\" x 10.5\" L, dual slot, full height", "mem": 32.0, "memType": "GDDR7", "bw": 896.0, "tdp": 200.0, "sms": null, "tc": 328.0, "cuda": 10496.0, "boost": 2407.0, "v": { "fp32": [ 51.0, null, "p" ], "fp64": [ 0.7969, null, "d" ], "tf32": [ 101.0625, 202.125, "d" ], "fp16": [ 202.125, 404.25, "d" ], "bf16": [ 202.125, 404.25, "d" ], "fp8": [ 404.25, 808.5, "d" ], "fp4": [ 808.5, 1617.0, "p" ], "int8": [ 404.25, 808.5, "d" ] }, "how": { "fp32": "NVIDIA: “Single-precision performance 51 TFLOPS1 | 1. Peak rates based on GPU Boost Clock.” [nvidia.com]", "fp64": "Derived: FP32 ÷ 64 (this architecture's FP64 rate)", "tf32": "Derived from NVIDIA's published FP4 figure of 808.5 dense. On RTX PRO Blackwell, TF32 runs at an eighth of the FP4 rate", "fp16": "Derived from NVIDIA's published FP4 figure of 808.5 dense. On RTX PRO Blackwell, FP16 runs at a quarter of the FP4 rate", "bf16": "Derived from NVIDIA's published FP4 figure of 808.5 dense. On RTX PRO Blackwell, BF16 runs at a quarter of the FP4 rate", "fp8": "Derived from NVIDIA's published FP4 figure of 808.5 dense. On RTX PRO Blackwell, FP8 runs at half the FP4 rate", "fp4": "NVIDIA: “AI TOPS 1,617 AI TOPS1,2 | 2. Effective FP4 TOPS with sparsity.” (dense = half the published sparse figure) [nvidia.com]", "int8": "Derived from NVIDIA's published FP4 figure of 808.5 dense. On RTX PRO Blackwell, INT8 runs at half the FP4 rate" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "fp6": "RTX Blackwell supports FP6, but NVIDIA publishes no FP6 rate for it", "int4": "NVIDIA lists no INT4 rate for Blackwell" }, "headline": "“AI TOPS 1,617 AI TOPS1,2 | 1. Peak rates based on GPU Boost Clock. 2. Effective FP4 TOPS with sparsity.” — read as FP4, sparse", "anchor": "Derived from NVIDIA's published FP4 figure of 808.5 dense. ", "notes": "Launch datasheet (Apr25, doc 3662540) listed no AI TOPS / FP32 / RT rows; first NVIDIA throughput figures appear in the Apr26 revision (doc 5108623). Product page still shows none.; Launch product page (Mar 2025 archive) gave 784 GB/sec bandwidth; all datasheets say 896 GB/s.", "sources": [ { "t": "nvidia.com — /content/dam/en-zz/Solutions/data-center/rtx-pro-4500-blackwell/workstation-data", "u": "https://www.nvidia.com/content/dam/en-zz/Solutions/data-center/rtx-pro-4500-blackwell/workstation-datasheet-blackwell-rtx-pro-4500-we-nvidia-us-5108623-web.pdf" }, { "t": "nvidia.com — /content/dam/en-zz/Solutions/data-center/rtx-pro-4500-blackwell/workstation-data", "u": "https://www.nvidia.com/content/dam/en-zz/Solutions/data-center/rtx-pro-4500-blackwell/workstation-datasheet-blackwell-rtx-pro-4500-gtc25-spring-nvidia-3662540.pdf" }, { "t": "nvidia.com — /en-us/products/workstations/professional-desktop-gpus/rtx-pro-4500/", "u": "https://www.nvidia.com/en-us/products/workstations/professional-desktop-gpus/rtx-pro-4500/" }, { "t": "web.archive.org — /web/20250322173407/https://www.nvidia.com/en-us/products/workstations/professio", "u": "https://web.archive.org/web/20250322173407/https://www.nvidia.com/en-us/products/workstations/professional-desktop-gpus/rtx-pro-4500/" }, { "t": "pny.com — /nvidia-rtx-pro-4500-blackwell-workstation-edition", "u": "https://www.pny.com/nvidia-rtx-pro-4500-blackwell-workstation-edition" }, { "t": "techpowerup.com — /gpu-specs/rtx-pro-4500-blackwell.c4278", "u": "https://www.techpowerup.com/gpu-specs/rtx-pro-4500-blackwell.c4278" } ], "aka": null }, { "id": "rtx-pro-5000-blackwell", "name": "NVIDIA RTX PRO 5000 Blackwell 48GB", "short": "RTX PRO 5000 Blackwell 48GB", "seg": "workstation", "arch": "Blackwell", "archGroup": "Blackwell", "cls": "blackwell-pro", "clsLabel": "Blackwell GB20x (RTX PRO)", "chip": "GB202", "date": "2025-03", "t": 2025.1666666666667, "status": null, "ff": "4.4\" x 10.5\" L, dual slot, full height", "mem": 48.0, "memType": "GDDR7", "bw": 1344.0, "tdp": 300.0, "sms": null, "tc": 440.0, "cuda": 14080.0, "boost": null, "v": { "fp32": [ 65.0, null, "p" ], "fp64": [ 1.0156, null, "d" ], "tf32": [ 129.0, 258.0, "d" ], "fp16": [ 258.0, 516.0, "d" ], "bf16": [ 258.0, 516.0, "d" ], "fp8": [ 516.0, 1032.0, "d" ], "fp4": [ 1032.0, 2064.0, "p" ], "int8": [ 516.0, 1032.0, "d" ] }, "how": { "fp32": "NVIDIA: “Single-Precision Performance 65 TFLOPS1 | 1. Peak rates based on GPU Boost Clock.” [nvidia.com]", "fp64": "Derived: FP32 ÷ 64 (this architecture's FP64 rate)", "tf32": "Derived from NVIDIA's published FP4 figure of 1,032 dense. On RTX PRO Blackwell, TF32 runs at an eighth of the FP4 rate", "fp16": "Derived from NVIDIA's published FP4 figure of 1,032 dense. On RTX PRO Blackwell, FP16 runs at a quarter of the FP4 rate", "bf16": "Derived from NVIDIA's published FP4 figure of 1,032 dense. On RTX PRO Blackwell, BF16 runs at a quarter of the FP4 rate", "fp8": "Derived from NVIDIA's published FP4 figure of 1,032 dense. On RTX PRO Blackwell, FP8 runs at half the FP4 rate", "fp4": "NVIDIA: “AI TOPS 2,064 AI TOPS1,2 | 2. Effective FP4 TOPS with sparsity.” (dense = half the published sparse figure) [nvidia.com]", "int8": "Derived from NVIDIA's published FP4 figure of 1,032 dense. On RTX PRO Blackwell, INT8 runs at half the FP4 rate" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "fp6": "RTX Blackwell supports FP6, but NVIDIA publishes no FP6 rate for it", "int4": "NVIDIA lists no INT4 rate for Blackwell" }, "headline": "“AI TOPS 2,064 AI TOPS1,2 | 1. Peak rates based on GPU Boost Clock. 2. Effective FP4 TOPS with sparsity.” — read as FP4, sparse", "anchor": "Derived from NVIDIA's published FP4 figure of 1,032 dense. ", "notes": "Datasheet (Jul26, doc 5349550) has one merged column for 48GB and 72GB variants (2,064 AI TOPS, 65 TFLOPS, 196 TFLOPS RT).; Jun26 revision of the same datasheet (still at the GTC25 URL) lists Memory Interface 512-bit; Jul26 revision and PNY say 384-bit (1,344 GB/s).; TechPowerUp's 2377 MHz boost does not match NVIDIA's 65 TFLOPS / 2,064 TOPS (those imply ~2.29-2.31 GHz); it does match the 2,142 TOPS NVIDIA's blog quotes for the 72GB model.", "sources": [ { "t": "nvidia.com — /content/dam/en-zz/Solutions/products/workstations/professional-desktop-gpus/rtx", "u": "https://www.nvidia.com/content/dam/en-zz/Solutions/products/workstations/professional-desktop-gpus/rtx-pro-5000-blackwell/workstation-datasheet-blackwell-rtx-pro-5000-5488550-nvidia.pdf" }, { "t": "nvidia.com — /content/dam/en-zz/Solutions/products/workstations/professional-desktop-gpus/rtx", "u": "https://www.nvidia.com/content/dam/en-zz/Solutions/products/workstations/professional-desktop-gpus/rtx-pro-5000-blackwell/workstation-datasheet-blackwell-rtx-pro-5000-gtc25-spring-nvidia-3658700.pdf" }, { "t": "nvidia.com — /en-us/products/workstations/professional-desktop-gpus/rtx-pro-5000/", "u": "https://www.nvidia.com/en-us/products/workstations/professional-desktop-gpus/rtx-pro-5000/" }, { "t": "pny.com — /nvidia-rtx-pro-5000-blackwell", "u": "https://www.pny.com/nvidia-rtx-pro-5000-blackwell" }, { "t": "nvidia.com — /content/dam/en-zz/Solutions/design-visualization/quadro-product-literature/pdf/", "u": "https://www.nvidia.com/content/dam/en-zz/Solutions/design-visualization/quadro-product-literature/pdf/NVIDIA-RTX-Blackwell-PRO-GPU-Architecture-v1_1.pdf" }, { "t": "techpowerup.com — /gpu-specs/rtx-pro-5000-blackwell.c4276", "u": "https://www.techpowerup.com/gpu-specs/rtx-pro-5000-blackwell.c4276" } ], "aka": null }, { "id": "rtx-pro-6000-blackwell-max-q", "name": "NVIDIA RTX PRO 6000 Blackwell Max-Q", "short": "RTX PRO 6000 Max-Q", "seg": "workstation", "arch": "Blackwell", "archGroup": "Blackwell", "cls": "blackwell-pro", "clsLabel": "Blackwell GB20x (RTX PRO)", "chip": "GB202", "date": "2025-03", "t": 2025.1666666666667, "status": null, "ff": "4.4\" x 10.5\" L, dual slot, full height; active (blower)", "mem": 96.0, "memType": "GDDR7", "bw": 1792.0, "tdp": 300.0, "sms": 188.0, "tc": 752.0, "cuda": 24064.0, "boost": 2280.0, "v": { "fp32": [ 109.7, null, "p" ], "fp64": [ 1.7141, null, "d" ], "tf32": [ 219.5, 438.9, "p" ], "fp16": [ 438.9, 877.9, "p" ], "bf16": [ 438.9, 877.9, "p" ], "fp8": [ 877.9, 1755.7, "p" ], "fp4": [ 1755.7, 3511.4, "p" ], "int8": [ 877.9, 1755.7, "p" ] }, "how": { "fp32": "NVIDIA: “Table 4, RTX PRO 6000 Blackwell Max-Q Workstation Edition: Peak FP32 TFLOPS (non-Tensor)¹ 109.7 | 1. Peak rates are based on GPU Boost Clock.” [nvidia.com]", "fp64": "Derived: FP32 ÷ 64 (this architecture's FP64 rate)", "tf32": "NVIDIA: “Table 4, RTX PRO 6000 Blackwell Max-Q Workstation Edition: Peak TF32 Tensor TFLOPS¹ 219.5/438.9²” [nvidia.com]", "fp16": "NVIDIA: “Table 4, RTX PRO 6000 Blackwell Max-Q Workstation Edition: Peak FP16 Tensor TFLOPS with FP32 Accumulate¹ 438.9/877.9²” [nvidia.com]", "bf16": "NVIDIA: “Table 4, RTX PRO 6000 Blackwell Max-Q Workstation Edition: Peak BF16 Tensor TFLOPS with FP32 Accumulate¹ 438.9/877.9²” [nvidia.com]", "fp8": "NVIDIA: “Table 4, RTX PRO 6000 Blackwell Max-Q Workstation Edition: Peak FP8 Tensor TFLOPS with FP32 Accumulate¹ 877.9/1755.7²” [nvidia.com]", "fp4": "NVIDIA: “Table 4, RTX PRO 6000 Blackwell Max-Q Workstation Edition: Peak FP4 Tensor TFLOPS with FP32 Accumulate (FP4 AI TOPS) 1755.7/3511.4² | 2. Effective TOPS / TFLOPS using the Sparsity Feature” [nvidia.com]", "int8": "NVIDIA: “Table 4, RTX PRO 6000 Blackwell Max-Q Workstation Edition: Peak INT8 Tensor TOPS¹ 877.9/1755.7²” [nvidia.com]" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "fp6": "RTX Blackwell supports FP6, but NVIDIA publishes no FP6 rate for it", "int4": "NVIDIA lists no INT4 rate for Blackwell" }, "headline": "“AI TOPS 3511 AI TOPS1,2 | 1 Peak rates based on GPU Boost Clock 2 Effective FP4 TOPS with sparsity” — read as FP4, sparse", "anchor": "Derived from NVIDIA's published FP16 figure of 438.9 dense. ", "notes": "Datasheet and product page round the whitepaper values (110 vs 109.7 TFLOPS FP32, 333 vs 332.6 RT, 3511 vs 3511.4 FP4 sparse); no real conflict.; Datasheet unchanged in throughput between Apr25 (doc 3519233) and Jun26 (doc 5349650).", "sources": [ { "t": "nvidia.com — /content/dam/en-zz/Solutions/products/workstations/professional-desktop-gpus/rtx", "u": "https://www.nvidia.com/content/dam/en-zz/Solutions/products/workstations/professional-desktop-gpus/rtx-pro-6000-max-q/workstation-datasheet-blackwell-rtx-pro-6000-max-q-nvidia-us-5349650-web.pdf" }, { "t": "nvidia.com — /content/dam/en-zz/Solutions/products/workstations/professional-desktop-gpus/rtx", "u": "https://www.nvidia.com/content/dam/en-zz/Solutions/products/workstations/professional-desktop-gpus/rtx-pro-6000-max-q/workstation-datasheet-blackwell-rtx-pro-6000-max-q-nvidia-3519233.pdf" }, { "t": "nvidia.com — /en-us/products/workstations/professional-desktop-gpus/rtx-pro-6000-max-q/", "u": "https://www.nvidia.com/en-us/products/workstations/professional-desktop-gpus/rtx-pro-6000-max-q/" }, { "t": "nvidia.com — /content/dam/en-zz/Solutions/design-visualization/quadro-product-literature/pdf/", "u": "https://www.nvidia.com/content/dam/en-zz/Solutions/design-visualization/quadro-product-literature/pdf/NVIDIA-RTX-Blackwell-PRO-GPU-Architecture-v1_1.pdf" }, { "t": "techpowerup.com — /gpu-specs/rtx-pro-6000-blackwell-max-q.c4273", "u": "https://www.techpowerup.com/gpu-specs/rtx-pro-6000-blackwell-max-q.c4273" } ], "aka": null }, { "id": "rtx-pro-6000-blackwell-workstation", "name": "NVIDIA RTX PRO 6000 Blackwell Workstation", "short": "RTX PRO 6000", "seg": "workstation", "arch": "Blackwell", "archGroup": "Blackwell", "cls": "blackwell-pro", "clsLabel": "Blackwell GB20x (RTX PRO)", "chip": "GB202", "date": "2025-03", "t": 2025.1666666666667, "status": null, "ff": "5.4\" H x 12\" L, dual slot, extended height; double flow-through", "mem": 96.0, "memType": "GDDR7", "bw": 1792.0, "tdp": 600.0, "sms": 188.0, "tc": 752.0, "cuda": 24064.0, "boost": 2617.0, "v": { "fp32": [ 126.0, null, "p" ], "fp64": [ 1.9688, null, "d" ], "tf32": [ 251.9, 503.8, "p" ], "fp16": [ 503.8, 1007.6, "p" ], "bf16": [ 503.8, 1007.6, "p" ], "fp8": [ 1007.6, 2015.2, "p" ], "fp4": [ 2015.2, 4030.4, "p" ], "int8": [ 1007.6, 2015.2, "p" ] }, "how": { "fp32": "NVIDIA: “Table 4, RTX PRO 6000 Blackwell Workstation Edition: Peak FP32 TFLOPS (non-Tensor)¹ 126.0 | 1. Peak rates are based on GPU Boost Clock.” [nvidia.com]", "fp64": "Derived: FP32 ÷ 64 (this architecture's FP64 rate)", "tf32": "NVIDIA: “Table 4, RTX PRO 6000 Blackwell Workstation Edition: Peak TF32 Tensor TFLOPS¹ 251.9/503.8²” [nvidia.com]", "fp16": "NVIDIA: “Table 4, RTX PRO 6000 Blackwell Workstation Edition: Peak FP16 Tensor TFLOPS with FP32 Accumulate¹ 503.8/1007.6²” [nvidia.com]", "bf16": "NVIDIA: “Table 4, RTX PRO 6000 Blackwell Workstation Edition: Peak BF16 Tensor TFLOPS with FP32 Accumulate¹ 503.8/1007.6²” [nvidia.com]", "fp8": "NVIDIA: “Table 4, RTX PRO 6000 Blackwell Workstation Edition: Peak FP8 Tensor TFLOPS with FP32 Accumulate¹ 1007.6/2015.2²” [nvidia.com]", "fp4": "NVIDIA: “Table 4, RTX PRO 6000 Blackwell Workstation Edition: Peak FP4 Tensor TFLOPS with FP32 Accumulate (FP4 AI TOPS) 2015.2/4030.4² | 2. Effective TOPS / TFLOPS using the Sparsity Feature” [nvidia.com]", "int8": "NVIDIA: “Table 4, RTX PRO 6000 Blackwell Workstation Edition: Peak INT8 Tensor TOPS¹ 1007.6/2015.2²” [nvidia.com]" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "fp6": "RTX Blackwell supports FP6, but NVIDIA publishes no FP6 rate for it", "int4": "NVIDIA lists no INT4 rate for Blackwell" }, "headline": "“AI TOPS 4000 AI TOPS1,2 | 1. Peak rates based on GPU Boost Clock. I 2. Effective FP4 TOPS with sparsity.” — read as FP4, sparse", "anchor": "Derived from NVIDIA's published FP16 figure of 503.8 dense. ", "notes": "CONFLICT (minor): FP32 125 TFLOPS (product page; Mar25/Apr25 datasheet) vs 126 (Jun26 datasheet) vs 126.0 (whitepaper); RT 380 vs 382 vs 381.8.; Headline 4000 AI TOPS is a rounded marketing figure; whitepaper gives FP4 2015.2 dense / 4030.4 sparse.; Server Edition (passive, data center) is a different SKU and is excluded.", "sources": [ { "t": "nvidia.com — /content/dam/en-zz/Solutions/data-center/rtx-pro-6000-blackwell-workstation-edit", "u": "https://www.nvidia.com/content/dam/en-zz/Solutions/data-center/rtx-pro-6000-blackwell-workstation-edition/workstation-blackwell-rtx-pro-6000-workstation-edition-nvidia-us-3519208-web.pdf" }, { "t": "web.archive.org — /web/20250318224351/https://www.nvidia.com/content/dam/en-zz/Solutions/data-cent", "u": "https://web.archive.org/web/20250318224351/https://www.nvidia.com/content/dam/en-zz/Solutions/data-center/rtx-pro-6000-blackwell-workstation-edition/workstation-blackwell-rtx-pro-6000-workstation-edition-nvidia-us-3519208-web.pdf" }, { "t": "nvidia.com — /en-us/products/workstations/professional-desktop-gpus/rtx-pro-6000/", "u": "https://www.nvidia.com/en-us/products/workstations/professional-desktop-gpus/rtx-pro-6000/" }, { "t": "nvidia.com — /content/dam/en-zz/Solutions/design-visualization/quadro-product-literature/pdf/", "u": "https://www.nvidia.com/content/dam/en-zz/Solutions/design-visualization/quadro-product-literature/pdf/NVIDIA-RTX-Blackwell-PRO-GPU-Architecture-v1_1.pdf" }, { "t": "techpowerup.com — /gpu-specs/rtx-pro-6000-blackwell.c4272", "u": "https://www.techpowerup.com/gpu-specs/rtx-pro-6000-blackwell.c4272" } ], "aka": null }, { "id": "rtx-2000e-ada", "name": "NVIDIA RTX 2000E Ada Generation", "short": "RTX 2000E Ada", "seg": "workstation", "arch": "Ada", "archGroup": "Ada", "cls": "ada-pro", "clsLabel": "Ada (RTX Ada, L4, L40S)", "chip": "AD107", "date": "2024-08", "t": 2024.5833333333333, "status": null, "ff": "2.7\" H x 6.6\" L, single slot", "mem": 16.0, "memType": "GDDR6", "bw": 224.0, "tdp": 50.0, "sms": null, "tc": 88.0, "cuda": 2816.0, "boost": null, "v": { "fp32": [ 8.9, null, "p" ], "fp64": [ 0.1391, null, "d" ], "tf32": [ 17.75, 35.5, "d" ], "fp16": [ 35.5, 71.0, "d" ], "bf16": [ 35.5, 71.0, "d" ], "fp8": [ 71.0, 142.0, "p" ], "int8": [ 71.0, 142.0, "d" ], "int4": [ 142.0, 284.0, "d" ] }, "how": { "fp32": "NVIDIA: “Single-precision performance 8.9 TFLOPS² | 2 Peak rates based on GPU Boost Clock.” [dam-cdn.nvd.orangelogic.com]", "fp64": "Derived: FP32 ÷ 64 (this architecture's FP64 rate)", "tf32": "Derived from NVIDIA's published FP8 figure of 71 dense. On workstation and data-centre Ada, TF32 runs at a quarter of the FP8 rate", "fp16": "Derived from NVIDIA's published FP8 figure of 71 dense. On workstation and data-centre Ada, FP16 runs at half the FP8 rate", "bf16": "Derived from NVIDIA's published FP8 figure of 71 dense. On workstation and data-centre Ada, BF16 runs at half the FP8 rate", "fp8": "NVIDIA: “Tensor (AI) performance 142 AI TOPS | 142 TFLOPS³ | 3 Theoretical FP8 TOPS and TFLOPS using the sparsity feature.” (dense = half the published sparse figure) [dam-cdn.nvd.orangelogic.com]", "int8": "Derived from NVIDIA's published FP8 figure of 71 dense. On workstation and data-centre Ada, INT8 runs at the same rate as FP8", "int4": "Derived from NVIDIA's published FP8 figure of 71 dense. On workstation and data-centre Ada, INT4 runs at twice the FP8 rate" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "fp6": "No FP6 tensor cores before Blackwell", "fp4": "No FP4 tensor cores before Blackwell" }, "headline": "“Tensor (AI) performance 142 AI TOPS | 142 TFLOPS³ | 3 Theoretical FP8 TOPS and TFLOPS using the sparsity feature.” — read as FP8, sparse", "anchor": "Derived from NVIDIA's published FP8 figure of 71 dense. ", "notes": "Datasheet revision Oct25 (doc 4328932). PCIe 4.0 x8 (full-length connector).; Boost clock not published by NVIDIA; TechPowerUp entry not located.", "sources": [ { "t": "dam-cdn.nvd.orangelogic.com — /AssetLink/0vje6015ixaxu83f5sc11r48p04000v2.pdf", "u": "https://dam-cdn.nvd.orangelogic.com/AssetLink/0vje6015ixaxu83f5sc11r48p04000v2.pdf" }, { "t": "resources.nvidia.com — /en-us-briefcase-for-datasheets/proviz-rtx-2000e-ada", "u": "https://resources.nvidia.com/en-us-briefcase-for-datasheets/proviz-rtx-2000e-ada" } ], "aka": null }, { "id": "rtx-a1000", "name": "NVIDIA RTX A1000", "short": "RTX A1000", "seg": "workstation", "arch": "Ampere", "archGroup": "Ampere", "cls": "ampere-pro", "clsLabel": "Ampere GA10x (RTX A, A10, A40)", "chip": "GA107", "date": "2024-04", "t": 2024.25, "status": null, "ff": "2.7\" H x 6.4\" L, single slot", "mem": 8.0, "memType": "GDDR6", "bw": 192.0, "tdp": 50.0, "sms": null, "tc": 72.0, "cuda": 2304.0, "boost": 1462.0, "v": { "fp32": [ 6.7, null, "p" ], "fp64": [ 0.1047, null, "d" ], "tf32": [ 13.45, 26.9, "d" ], "fp16": [ 26.9, 53.8, "p" ], "bf16": [ 26.9, 53.8, "d" ], "int8": [ 53.9, 107.8, "p" ], "int4": [ 107.6, 215.2, "d" ] }, "how": { "fp32": "NVIDIA: “Single-precision performance 6.7 TFLOPS² | 2 Peak rates based on GPU Boost Clock.” [dam-cdn.nvd.orangelogic.com]", "fp64": "Derived: FP32 ÷ 64 (this architecture's FP64 rate)", "tf32": "Derived from NVIDIA's published FP16 figure of 26.9 dense. On workstation and data-centre Ampere, TF32 runs at half the FP16 rate", "fp16": "NVIDIA: “FP16 Tensor performance 53.8 TFLOPS³ | 3 Effective FP16 teraFLOPS (TFLOPS) using the sparsity feature.” (dense = half the published sparse figure) [dam-cdn.nvd.orangelogic.com]", "bf16": "Derived from NVIDIA's published FP16 figure of 26.9 dense. On workstation and data-centre Ampere, BF16 runs at the same rate as FP16", "int8": "NVIDIA: “Peak INT8 Tensor performance 107.8 TOPS⁴ | 4 Peak INT8 TOPS with sparsity.” (dense = half the published sparse figure) [dam-cdn.nvd.orangelogic.com]", "int4": "Derived from NVIDIA's published FP16 figure of 26.9 dense. On workstation and data-centre Ampere, INT4 runs at 4× the FP16 rate" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "fp8": "No FP8 tensor cores before Ada/Hopper (FP8 models run at FP16 speed)", "fp6": "No FP6 tensor cores before Blackwell", "fp4": "No FP4 tensor cores before Blackwell" }, "headline": "“Tensor Performance 53.8 TFLOPS1,2 | 2. Effective FP16 teraFLOPS (TFLOPS) using the sparsity feature.” — read as FP16, sparse", "anchor": "Derived from NVIDIA's published FP16 figure of 26.9 dense. ", "notes": "Datasheet dated APR24. Product page headline is FP16 (unlike RTX A400, whose page headline is INT8).", "sources": [ { "t": "dam-cdn.nvd.orangelogic.com — /AssetLink/3go5lvr2vupn73or2e662t7h6g1b36l1.pdf", "u": "https://dam-cdn.nvd.orangelogic.com/AssetLink/3go5lvr2vupn73or2e662t7h6g1b36l1.pdf" }, { "t": "nvidia.com — /en-us/products/workstations/rtx-a1000/", "u": "https://www.nvidia.com/en-us/products/workstations/rtx-a1000/" }, { "t": "blogs.nvidia.com — /blog/ampere-rtx-a400-a1000-ai/", "u": "https://blogs.nvidia.com/blog/ampere-rtx-a400-a1000-ai/" }, { "t": "techpowerup.com — /gpu-specs/rtx-a1000.c4211", "u": "https://www.techpowerup.com/gpu-specs/rtx-a1000.c4211" } ], "aka": null }, { "id": "rtx-a400", "name": "NVIDIA RTX A400", "short": "RTX A400", "seg": "workstation", "arch": "Ampere", "archGroup": "Ampere", "cls": "ampere-pro", "clsLabel": "Ampere GA10x (RTX A, A10, A40)", "chip": "GA107", "date": "2024-04", "t": 2024.25, "status": null, "ff": "2.7\" H x 6.4\" L, single slot", "mem": 4.0, "memType": "GDDR6", "bw": 96.0, "tdp": 50.0, "sms": null, "tc": 24.0, "cuda": 768.0, "boost": 1762.0, "v": { "fp32": [ 2.7, null, "p" ], "fp64": [ 0.0422, null, "d" ], "tf32": [ 5.425, 10.85, "d" ], "fp16": [ 10.85, 21.7, "p" ], "bf16": [ 10.85, 21.7, "d" ], "int8": [ 21.65, 43.3, "p" ], "int4": [ 43.4, 86.8, "d" ] }, "how": { "fp32": "NVIDIA: “Single-precision performance 2.7 TFLOPS² | 2 Peak rates based on GPU Boost Clock.” [dam-cdn.nvd.orangelogic.com]", "fp64": "Derived: FP32 ÷ 64 (this architecture's FP64 rate)", "tf32": "Derived from NVIDIA's published FP16 figure of 10.85 dense. On workstation and data-centre Ampere, TF32 runs at half the FP16 rate", "fp16": "NVIDIA: “FP16 Tensor performance 21.7 TFLOPS³ | 3 Effective FP16 teraFLOPS (TFLOPS) using the sparsity feature.” (dense = half the published sparse figure) [dam-cdn.nvd.orangelogic.com]", "bf16": "Derived from NVIDIA's published FP16 figure of 10.85 dense. On workstation and data-centre Ampere, BF16 runs at the same rate as FP16", "int8": "NVIDIA: “Peak INT8 Tensor performance 43.3 TOPS⁴ | 4 Peak ITN8 TOPS with sparsity. [sic]” (dense = half the published sparse figure) [dam-cdn.nvd.orangelogic.com]", "int4": "Derived from NVIDIA's published FP16 figure of 10.85 dense. On workstation and data-centre Ampere, INT4 runs at 4× the FP16 rate" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "fp8": "No FP8 tensor cores before Ada/Hopper (FP8 models run at FP16 speed)", "fp6": "No FP6 tensor cores before Blackwell", "fp4": "No FP4 tensor cores before Blackwell" }, "headline": "“Tensor Performance 43.3 TOPS² | 2. Effective INT8 trillion operations per second (TOPS) using the sparsity feature.” — read as INT8, sparse", "anchor": "Derived from NVIDIA's published FP16 figure of 10.85 dense. ", "notes": "Product page headline is INT8 (43.3 TOPS sparse) while the datasheet lists both FP16 (21.7 sparse) and INT8 rows.; Product page RT Core Performance 5.3 TFLOPS vs datasheet 5.4 TFLOPS (minor NVIDIA inconsistency).; Datasheet dated May24 (doc 3279761); identical file also served via NVIDIA's datasheet briefcase.", "sources": [ { "t": "dam-cdn.nvd.orangelogic.com — /AssetLink/k28c3b6382sbi8n8jxl686l4ka3816p8.pdf", "u": "https://dam-cdn.nvd.orangelogic.com/AssetLink/k28c3b6382sbi8n8jxl686l4ka3816p8.pdf" }, { "t": "nvidia.com — /en-us/products/workstations/rtx-a400/", "u": "https://www.nvidia.com/en-us/products/workstations/rtx-a400/" }, { "t": "blogs.nvidia.com — /blog/ampere-rtx-a400-a1000-ai/", "u": "https://blogs.nvidia.com/blog/ampere-rtx-a400-a1000-ai/" }, { "t": "techpowerup.com — /gpu-specs/rtx-a400.c4212", "u": "https://www.techpowerup.com/gpu-specs/rtx-a400.c4212" } ], "aka": null }, { "id": "rtx-2000-ada", "name": "NVIDIA RTX 2000 Ada Generation", "short": "RTX 2000 Ada", "seg": "workstation", "arch": "Ada", "archGroup": "Ada", "cls": "ada-pro", "clsLabel": "Ada (RTX Ada, L4, L40S)", "chip": "AD107", "date": "2024-02", "t": 2024.0833333333333, "status": null, "ff": "2.7\" H x 6.6\" L, dual slot", "mem": 16.0, "memType": "GDDR6", "bw": 224.0, "tdp": 70.0, "sms": null, "tc": 88.0, "cuda": 2816.0, "boost": 2130.0, "v": { "fp32": [ 12.0, null, "p" ], "fp64": [ 0.1875, null, "d" ], "tf32": [ 23.9875, 47.975, "d" ], "fp16": [ 47.975, 95.95, "d" ], "bf16": [ 47.975, 95.95, "d" ], "fp8": [ 95.95, 191.9, "p" ], "int8": [ 95.95, 191.9, "d" ], "int4": [ 191.9, 383.8, "d" ] }, "how": { "fp32": "NVIDIA: “单精度浮点运算性能 12.0 TFLOPS2 | 2 峰值速率基于 GPU 加速频率 [English, NVIDIA product page: 'Single-Precision Performance 12.0 TFLOPS¹ | 1 Peak rates based on GPU Boost Clock']” [nvidia.cn]", "fp64": "Derived: FP32 ÷ 64 (this architecture's FP64 rate)", "tf32": "Derived from NVIDIA's published FP8 figure of 95.95 dense. On workstation and data-centre Ada, TF32 runs at a quarter of the FP8 rate", "fp16": "Derived from NVIDIA's published FP8 figure of 95.95 dense. On workstation and data-centre Ada, FP16 runs at half the FP8 rate", "bf16": "Derived from NVIDIA's published FP8 figure of 95.95 dense. On workstation and data-centre Ada, BF16 runs at half the FP8 rate", "fp8": "NVIDIA: “Tensor 性能 191.9 TFLOPS3 | 3 使用稀疏功能的有效 FP8 teraFLOPS (TFLOPS) ['Effective FP8 teraFLOPS (TFLOPS) using the sparsity feature']” (dense = half the published sparse figure) [nvidia.cn]", "int8": "Derived from NVIDIA's published FP8 figure of 95.95 dense. On workstation and data-centre Ada, INT8 runs at the same rate as FP8", "int4": "Derived from NVIDIA's published FP8 figure of 95.95 dense. On workstation and data-centre Ada, INT4 runs at twice the FP8 rate" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "fp6": "No FP6 tensor cores before Blackwell", "fp4": "No FP4 tensor cores before Blackwell" }, "headline": "“Tensor Performance 191.9 TFLOPS² | 1 Peak rates based on GPU Boost Clock | 2 Effective FP8 teraFLOPS (TFLOPS) using the sparsity feature.” — read as FP8, sparse", "anchor": "Derived from NVIDIA's published FP8 figure of 95.95 dense. ", "notes": "English NVIDIA datasheet not found on nvidia.com; NVIDIA China (zhCN, doc 3169852, Feb 2024) used, plus HP-hosted copy of the English datasheet (doc 2999417, Jan24) with identical numbers.", "sources": [ { "t": "nvidia.com — /en-us/products/workstations/rtx-2000/", "u": "https://www.nvidia.com/en-us/products/workstations/rtx-2000/" }, { "t": "nvidia.cn — /content/dam/en-zz/Solutions/design-visualization/rtx-2000/proviz-rtx-2000-ada-d", "u": "https://www.nvidia.cn/content/dam/en-zz/Solutions/design-visualization/rtx-2000/proviz-rtx-2000-ada-datasheet-zhCN-3169852-print.pdf" }, { "t": "valuehub.hp.com — /static/nvidia/docs/NVIDIA%20RTX%202000%20Ada%20Generation%20Datasheet.pdf", "u": "https://valuehub.hp.com/static/nvidia/docs/NVIDIA%20RTX%202000%20Ada%20Generation%20Datasheet.pdf" }, { "t": "blogs.nvidia.com — /blog/rtx-2000-ada/", "u": "https://blogs.nvidia.com/blog/rtx-2000-ada/" }, { "t": "techpowerup.com — /gpu-specs/rtx-2000-ada-generation.c4199", "u": "https://www.techpowerup.com/gpu-specs/rtx-2000-ada-generation.c4199" } ], "aka": null, "measured": { "best": { "fp32": { "value": 6.0, "unit": "TFLOPS", "sm_mhz": 1710.0, "power_w": 69.3 }, "tf32": { "value": 17.14, "unit": "TFLOPS", "sm_mhz": 1635.0, "power_w": 69.4 }, "fp16": { "value": 35.46, "unit": "TFLOPS", "sm_mhz": 1665.0, "power_w": 69.4 }, "fp16_acc16": { "value": 38.49, "unit": "TFLOPS", "sm_mhz": 1755.0, "power_w": 69.3 }, "bf16": { "value": 36.4, "unit": "TFLOPS", "sm_mhz": 1710.0, "power_w": 69.6 }, "fp8": { "value": 73.76, "unit": "TFLOPS", "sm_mhz": 1740.0, "power_w": 69.5 }, "fp8_fastacc": { "value": 79.21, "unit": "TFLOPS", "sm_mhz": 1800.0, "power_w": 68.8 }, "int8": { "value": 83.85, "unit": "TOPS", "sm_mhz": 1980.0, "power_w": 68.4 }, "fp64": { "value": 0.19, "unit": "TFLOPS", "sm_mhz": 2415.0, "power_w": 28.4 }, "dram": { "value": 206.57, "unit": "GB/s", "sm_mhz": 2415.0, "power_w": 45.6 } } } }, { "id": "rtx-5880-ada", "name": "NVIDIA RTX 5880 Ada Generation", "short": "RTX 5880 Ada", "seg": "workstation", "arch": "Ada", "archGroup": "Ada", "cls": "ada-pro", "clsLabel": "Ada (RTX Ada, L4, L40S)", "chip": "AD102", "date": "2024-01", "t": 2024.0, "status": null, "ff": "4.4\" H x 10.5\" L, dual slot", "mem": 48.0, "memType": "GDDR6", "bw": 960.0, "tdp": 285.0, "sms": null, "tc": 440.0, "cuda": 14080.0, "boost": 2460.0, "v": { "fp32": [ 69.3, null, "p" ], "fp64": [ 1.0828, null, "d" ], "tf32": [ 138.55, 277.1, "d" ], "fp16": [ 277.1, 554.2, "d" ], "bf16": [ 277.1, 554.2, "d" ], "fp8": [ 554.2, 1108.4, "p" ], "int8": [ 554.2, 1108.4, "d" ], "int4": [ 1108.4, 2216.8, "d" ] }, "how": { "fp32": "NVIDIA: “单精度性能 69.3 TFLOPS3 | 3. 峰值速率基于 GPU 加速频率 [English product page: 'Single-Precision Performance 69.3 TFLOPS¹']” [nvidia.cn]", "fp64": "Derived: FP32 ÷ 64 (this architecture's FP64 rate)", "tf32": "Derived from NVIDIA's published FP8 figure of 554.2 dense. On workstation and data-centre Ada, TF32 runs at a quarter of the FP8 rate", "fp16": "Derived from NVIDIA's published FP8 figure of 554.2 dense. On workstation and data-centre Ada, FP16 runs at half the FP8 rate", "bf16": "Derived from NVIDIA's published FP8 figure of 554.2 dense. On workstation and data-centre Ada, BF16 runs at half the FP8 rate", "fp8": "NVIDIA: “Tensor 性能 1108.4 TFLOPS4 | 4. 使用稀疏技术的有效 FP8 teraFLOPS (TFLOPS) [HP-hosted English copy: '4 Effective FP8 teraFLOPS (TFLOPS) using sparsity.']” (dense = half the published sparse figure) [nvidia.cn]", "int8": "Derived from NVIDIA's published FP8 figure of 554.2 dense. On workstation and data-centre Ada, INT8 runs at the same rate as FP8", "int4": "Derived from NVIDIA's published FP8 figure of 554.2 dense. On workstation and data-centre Ada, INT4 runs at twice the FP8 rate" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "fp6": "No FP6 tensor cores before Blackwell", "fp4": "No FP4 tensor cores before Blackwell" }, "headline": "“Tensor 性能 1108.4 TFLOPS4 | 4. 使用稀疏技术的有效 FP8 teraFLOPS (TFLOPS) (= 'Effective FP8 TFLOPS using sparsity')” — read as FP8, sparse", "anchor": "Derived from NVIDIA's published FP8 figure of 554.2 dense. ", "notes": "English NVIDIA datasheet not found on nvidia.com; NVIDIA China zhCN datasheet (doc 3082478, Dec 2023) used; HP-hosted English copy (doc 3156635, Feb24) has identical numbers. Card was positioned for markets incl. China.", "sources": [ { "t": "nvidia.cn — /content/dam/en-zz/Solutions/design-visualization/rtx-5880/proviz-rtx-5880-ada-d", "u": "https://www.nvidia.cn/content/dam/en-zz/Solutions/design-visualization/rtx-5880/proviz-rtx-5880-ada-datasheet-print-zhCN-3082478.pdf" }, { "t": "valuehub.hp.com — /static/nvidia/docs/NVIDIA%20RTX%205880%20Ada%20Generation%20Datasheet.pdf", "u": "https://valuehub.hp.com/static/nvidia/docs/NVIDIA%20RTX%205880%20Ada%20Generation%20Datasheet.pdf" }, { "t": "nvidia.com — /en-us/products/workstations/rtx-5880/", "u": "https://www.nvidia.com/en-us/products/workstations/rtx-5880/" }, { "t": "techpowerup.com — /gpu-specs/rtx-5880-ada-generation.c4191", "u": "https://www.techpowerup.com/gpu-specs/rtx-5880-ada-generation.c4191" } ], "aka": null }, { "id": "a800-40gb-active", "name": "NVIDIA A800 40GB Active", "short": "A800 40GB Active", "seg": "workstation", "arch": "Ampere", "archGroup": "Ampere", "cls": "ampere-ga100", "clsLabel": "Ampere GA100 (A100, A30)", "chip": "GA100", "date": "2023-11", "t": 2023.8333333333333, "status": null, "ff": "4.4\" H x 10.5\" L, dual slot; active; no display outputs", "mem": 40.0, "memType": "HBM2", "bw": 1555.2, "tdp": 240.0, "sms": null, "tc": 432.0, "cuda": 6912.0, "boost": null, "v": { "fp32": [ 19.5, null, "p" ], "fp64": [ 9.7, null, "p" ], "fp64tc": [ 19.4844, null, "d" ], "tf32": [ 155.875, 311.75, "d" ], "fp16": [ 311.75, 623.5, "d" ], "bf16": [ 311.75, 623.5, "d" ], "int8": [ 623.5, 1247.0, "p" ], "int4": [ 1247.0, 2494.0, "d" ] }, "how": { "fp32": "NVIDIA: “Single-Precision Performance 19.5 TFLOPS” [nvidia.com]", "fp64": "NVIDIA: “Double-Precision Performance 9.7 TFLOPS” [nvidia.com]", "fp64tc": "Derived from NVIDIA's published INT8 figure of 623.5 dense. On GA100, FP64 TC runs at 0.03125× the INT8 rate", "tf32": "Derived from NVIDIA's published INT8 figure of 623.5 dense. On GA100, TF32 runs at a quarter of the INT8 rate", "fp16": "Derived from NVIDIA's published INT8 figure of 623.5 dense. On GA100, FP16 runs at half the INT8 rate", "bf16": "Derived from NVIDIA's published INT8 figure of 623.5 dense. On GA100, BF16 runs at half the INT8 rate", "int8": "NVIDIA: “Tensor Performance 1,247 AI TOPS² | 2 Theoretical INT8 TOPS using sparsity.” (dense = half the published sparse figure) [nvidia.com]", "int4": "Derived from NVIDIA's published INT8 figure of 623.5 dense. On GA100, INT4 runs at twice the INT8 rate" }, "na": { "fp8": "No FP8 tensor cores before Ada/Hopper (FP8 models run at FP16 speed)", "fp6": "No FP6 tensor cores before Blackwell", "fp4": "No FP4 tensor cores before Blackwell" }, "headline": "“Peak Tensor Performance 623.8 TFLOPS (no footnote)”", "anchor": "Derived from NVIDIA's published INT8 figure of 623.5 dense. ", "notes": "Headline precision/sparsity unclear on the datasheet; 623.8 TFLOPS is not footnoted anywhere by NVIDIA.; NVIDIA does not publish TF32, FP16, BF16 or FP64-Tensor rates for this card in the documents checked.; MIG up to 7 instances @ 5GB; NVLink 400 GB/s; boost clock not published by NVIDIA (TechPowerUp entry not located).", "sources": [ { "t": "nvidia.com — /content/dam/en-zz/Solutions/products/workstations/nvidia-a800-40gb-active-datas", "u": "https://www.nvidia.com/content/dam/en-zz/Solutions/products/workstations/nvidia-a800-40gb-active-datasheet.pdf" }, { "t": "nvidia.com — /en-us/products/workstations/a800/", "u": "https://www.nvidia.com/en-us/products/workstations/a800/" } ], "aka": null }, { "id": "rtx-4000-ada", "name": "NVIDIA RTX 4000 Ada Generation", "short": "RTX 4000 Ada", "seg": "workstation", "arch": "Ada", "archGroup": "Ada", "cls": "ada-pro", "clsLabel": "Ada (RTX Ada, L4, L40S)", "chip": "AD104", "date": "2023-08", "t": 2023.5833333333333, "status": null, "ff": "4.4\" H x 9.5\" L, single slot", "mem": 20.0, "memType": "GDDR6", "bw": 360.0, "tdp": 130.0, "sms": null, "tc": 192.0, "cuda": 6144.0, "boost": 2175.0, "v": { "fp32": [ 26.7, null, "p" ], "fp64": [ 0.4172, null, "d" ], "tf32": [ 53.45, 106.9, "d" ], "fp16": [ 106.9, 213.8, "d" ], "bf16": [ 106.9, 213.8, "d" ], "fp8": [ 213.8, 427.6, "p" ], "int8": [ 213.8, 427.6, "d" ], "int4": [ 427.6, 855.2, "d" ] }, "how": { "fp32": "NVIDIA: “Single-Precision Performance 26.7 TFLOPS³ | 3 Peak rates based on GPU boost clock.” [nvidia.com]", "fp64": "Derived: FP32 ÷ 64 (this architecture's FP64 rate)", "tf32": "Derived from NVIDIA's published FP8 figure of 213.8 dense. On workstation and data-centre Ada, TF32 runs at a quarter of the FP8 rate", "fp16": "Derived from NVIDIA's published FP8 figure of 213.8 dense. On workstation and data-centre Ada, FP16 runs at half the FP8 rate", "bf16": "Derived from NVIDIA's published FP8 figure of 213.8 dense. On workstation and data-centre Ada, BF16 runs at half the FP8 rate", "fp8": "NVIDIA: “Tensor Performance 427.6 TFLOPS (FP8 with sparsity; the datasheet says 327.6)” (dense = half the published sparse figure) [nvidia.com]", "int8": "Derived from NVIDIA's published FP8 figure of 213.8 dense. On workstation and data-centre Ada, INT8 runs at the same rate as FP8", "int4": "Derived from NVIDIA's published FP8 figure of 213.8 dense. On workstation and data-centre Ada, INT4 runs at twice the FP8 rate" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "fp6": "No FP6 tensor cores before Blackwell", "fp4": "No FP4 tensor cores before Blackwell" }, "headline": "“Tensor Performance 427.6 TFLOPS (product page; the datasheet's 327.6 looks like a typo)” — read as FP8, sparse", "anchor": "Derived from NVIDIA's published FP8 figure of 213.8 dense. ", "notes": "NVIDIA's documents disagree: the datasheet says 327.6 TFLOPS (FP8, sparse) and the product page 427.6. The page uses 427.6, which matches the card's own 26.7 TFLOPS FP32 at the same 16:1 ratio as every other Ada workstation card, so 327.6 looks like a datasheet typo.", "sources": [ { "t": "nvidia.com — /content/dam/en-zz/Solutions/products/workstations/nvidia-rtx-4000-datasheet.pdf", "u": "https://www.nvidia.com/content/dam/en-zz/Solutions/products/workstations/nvidia-rtx-4000-datasheet.pdf" }, { "t": "nvidia.com — /en-us/products/workstations/rtx-4000/", "u": "https://www.nvidia.com/en-us/products/workstations/rtx-4000/" }, { "t": "techpowerup.com — /gpu-specs/rtx-4000-ada-generation.c4171", "u": "https://www.techpowerup.com/gpu-specs/rtx-4000-ada-generation.c4171" } ], "aka": null }, { "id": "rtx-4500-ada", "name": "NVIDIA RTX 4500 Ada Generation", "short": "RTX 4500 Ada", "seg": "workstation", "arch": "Ada", "archGroup": "Ada", "cls": "ada-pro", "clsLabel": "Ada (RTX Ada, L4, L40S)", "chip": "AD104", "date": "2023-08", "t": 2023.5833333333333, "status": null, "ff": "4.4\" H x 10.5\" L, dual slot", "mem": 24.0, "memType": "GDDR6", "bw": 432.0, "tdp": 210.0, "sms": null, "tc": 240.0, "cuda": 7680.0, "boost": 2580.0, "v": { "fp32": [ 39.6, null, "p" ], "fp64": [ 0.6188, null, "d" ], "tf32": [ 79.25, 158.5, "d" ], "fp16": [ 158.5, 317.0, "d" ], "bf16": [ 158.5, 317.0, "d" ], "fp8": [ 317.0, 634.0, "p" ], "int8": [ 317.0, 634.0, "d" ], "int4": [ 634.0, 1268.0, "d" ] }, "how": { "fp32": "NVIDIA: “Single-Precision Performance 39.6 TFLOPS³ | 3 Peak rates based on GPU boost clock.” [nvidia.com]", "fp64": "Derived: FP32 ÷ 64 (this architecture's FP64 rate)", "tf32": "Derived from NVIDIA's published FP8 figure of 317 dense. On workstation and data-centre Ada, TF32 runs at a quarter of the FP8 rate", "fp16": "Derived from NVIDIA's published FP8 figure of 317 dense. On workstation and data-centre Ada, FP16 runs at half the FP8 rate", "bf16": "Derived from NVIDIA's published FP8 figure of 317 dense. On workstation and data-centre Ada, BF16 runs at half the FP8 rate", "fp8": "NVIDIA: “Tensor Performance 634.0 TFLOPS⁴ | 4 Effective FP8 teraFLOPS (TFLOPS) using sparsity.” (dense = half the published sparse figure) [nvidia.com]", "int8": "Derived from NVIDIA's published FP8 figure of 317 dense. On workstation and data-centre Ada, INT8 runs at the same rate as FP8", "int4": "Derived from NVIDIA's published FP8 figure of 317 dense. On workstation and data-centre Ada, INT4 runs at twice the FP8 rate" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "fp6": "No FP6 tensor cores before Blackwell", "fp4": "No FP4 tensor cores before Blackwell" }, "headline": "“Tensor Performance 634.0 TFLOPS⁴ | 4 Effective FP8 teraFLOPS (TFLOPS) using sparsity.” — read as FP8, sparse", "anchor": "Derived from NVIDIA's published FP8 figure of 317 dense. ", "notes": "Datasheet dated OCT23 (doc 2895216). Product page shows 634.0 TFLOPS with only the boost-clock footnote (no precision).", "sources": [ { "t": "nvidia.com — /content/dam/en-zz/Solutions/products/workstations/nvidia-rtx-4500-datasheet.pdf", "u": "https://www.nvidia.com/content/dam/en-zz/Solutions/products/workstations/nvidia-rtx-4500-datasheet.pdf" }, { "t": "nvidia.com — /en-us/products/workstations/rtx-4500/", "u": "https://www.nvidia.com/en-us/products/workstations/rtx-4500/" }, { "t": "techpowerup.com — /gpu-specs/rtx-4500-ada-generation.c4172", "u": "https://www.techpowerup.com/gpu-specs/rtx-4500-ada-generation.c4172" } ], "aka": null }, { "id": "rtx-5000-ada", "name": "NVIDIA RTX 5000 Ada Generation", "short": "RTX 5000 Ada", "seg": "workstation", "arch": "Ada", "archGroup": "Ada", "cls": "ada-pro", "clsLabel": "Ada (RTX Ada, L4, L40S)", "chip": "AD102", "date": "2023-08", "t": 2023.5833333333333, "status": null, "ff": "4.4\" H x 10.5\" L, dual slot", "mem": 32.0, "memType": "GDDR6", "bw": 576.0, "tdp": 250.0, "sms": null, "tc": 400.0, "cuda": 12800.0, "boost": 2550.0, "v": { "fp32": [ 65.3, null, "p" ], "fp64": [ 1.0203, null, "d" ], "tf32": [ 130.55, 261.1, "d" ], "fp16": [ 261.1, 522.2, "d" ], "bf16": [ 261.1, 522.2, "d" ], "fp8": [ 522.2, 1044.4, "p" ], "int8": [ 522.2, 1044.4, "d" ], "int4": [ 1044.4, 2088.8, "d" ] }, "how": { "fp32": "NVIDIA: “Single-Precision Performance 65.3 TFLOPS³ | 3 Peak rates based on GPU boost clock.” [cdn.pathfactory.com]", "fp64": "Derived: FP32 ÷ 64 (this architecture's FP64 rate)", "tf32": "Derived from NVIDIA's published FP8 figure of 522.2 dense. On workstation and data-centre Ada, TF32 runs at a quarter of the FP8 rate", "fp16": "Derived from NVIDIA's published FP8 figure of 522.2 dense. On workstation and data-centre Ada, FP16 runs at half the FP8 rate", "bf16": "Derived from NVIDIA's published FP8 figure of 522.2 dense. On workstation and data-centre Ada, BF16 runs at half the FP8 rate", "fp8": "NVIDIA: “Tensor Performance 1044.4 TFLOPS⁴ | 4 Effective FP8 teraFLOPS (TFLOPS) using sparsity.” (dense = half the published sparse figure) [cdn.pathfactory.com]", "int8": "Derived from NVIDIA's published FP8 figure of 522.2 dense. On workstation and data-centre Ada, INT8 runs at the same rate as FP8", "int4": "Derived from NVIDIA's published FP8 figure of 522.2 dense. On workstation and data-centre Ada, INT4 runs at twice the FP8 rate" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "fp6": "No FP6 tensor cores before Blackwell", "fp4": "No FP4 tensor cores before Blackwell" }, "headline": "“Tensor Performance 1044.4 TFLOPS⁴ | 4 Effective FP8 teraFLOPS (TFLOPS) using sparsity.” — read as FP8, sparse", "anchor": "Derived from NVIDIA's published FP8 figure of 522.2 dense. ", "notes": "Datasheet dated Aug23 (doc 2898211), served via NVIDIA's datasheet briefcase (resources.nvidia.com). Product page shows 1,044.4 TFLOPS without a precision footnote.", "sources": [ { "t": "cdn.pathfactory.com — /assets/10412/contents/1095460/b57d512c-c1b8-4fea-b9e5-cb95bcb33c44.pdf", "u": "https://cdn.pathfactory.com/assets/10412/contents/1095460/b57d512c-c1b8-4fea-b9e5-cb95bcb33c44.pdf" }, { "t": "resources.nvidia.com — /en-us-briefcase-for-datasheets/rtx-5000-ada-datashe", "u": "https://resources.nvidia.com/en-us-briefcase-for-datasheets/rtx-5000-ada-datashe" }, { "t": "nvidia.com — /en-us/products/workstations/rtx-5000/", "u": "https://www.nvidia.com/en-us/products/workstations/rtx-5000/" }, { "t": "techpowerup.com — /gpu-specs/rtx-5000-ada-generation.c4152", "u": "https://www.techpowerup.com/gpu-specs/rtx-5000-ada-generation.c4152" } ], "aka": null }, { "id": "rtx-4000-sff-ada", "name": "NVIDIA RTX 4000 SFF Ada Generation", "short": "RTX 4000 SFF Ada", "seg": "workstation", "arch": "Ada", "archGroup": "Ada", "cls": "ada-pro", "clsLabel": "Ada (RTX Ada, L4, L40S)", "chip": "AD104", "date": "2023-03", "t": 2023.1666666666667, "status": null, "ff": "2.7\" H x 6.6\" L, dual slot", "mem": 20.0, "memType": "GDDR6", "bw": 280.0, "tdp": 70.0, "sms": null, "tc": 192.0, "cuda": 6144.0, "boost": 1560.0, "v": { "fp32": [ 19.2, null, "p" ], "fp64": [ 0.3, null, "d" ], "tf32": [ 38.35, 76.7, "d" ], "fp16": [ 76.7, 153.4, "d" ], "bf16": [ 76.7, 153.4, "d" ], "fp8": [ 153.4, 306.8, "p" ], "int8": [ 153.4, 306.8, "d" ], "int4": [ 306.8, 613.6, "d" ] }, "how": { "fp32": "NVIDIA: “Single-precision performance 19.2 TFLOPS³ | 3 Peak rates based on GPU Boost Clock.” [nvidia.com]", "fp64": "Derived: FP32 ÷ 64 (this architecture's FP64 rate)", "tf32": "Derived from NVIDIA's published FP8 figure of 153.4 dense. On workstation and data-centre Ada, TF32 runs at a quarter of the FP8 rate", "fp16": "Derived from NVIDIA's published FP8 figure of 153.4 dense. On workstation and data-centre Ada, FP16 runs at half the FP8 rate", "bf16": "Derived from NVIDIA's published FP8 figure of 153.4 dense. On workstation and data-centre Ada, BF16 runs at half the FP8 rate", "fp8": "NVIDIA: “Tensor performance 306.8 TFLOPS⁴ | 4 Effective FP8 teraFLOPS (TFLOPS) using the sparsity feature.” (dense = half the published sparse figure) [nvidia.com]", "int8": "Derived from NVIDIA's published FP8 figure of 153.4 dense. On workstation and data-centre Ada, INT8 runs at the same rate as FP8", "int4": "Derived from NVIDIA's published FP8 figure of 153.4 dense. On workstation and data-centre Ada, INT4 runs at twice the FP8 rate" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "fp6": "No FP6 tensor cores before Blackwell", "fp4": "No FP4 tensor cores before Blackwell" }, "headline": "“Tensor performance 306.8 TFLOPS⁴ | 4 Effective FP8 teraFLOPS (TFLOPS) using the sparsity feature.” — read as FP8, sparse", "anchor": "Derived from NVIDIA's published FP8 figure of 153.4 dense. ", "notes": "Datasheet dated APR23 (doc 2742450). Product page rounds to '307 AI TOPS' (FP8 sparse).", "sources": [ { "t": "nvidia.com — /content/dam/en-zz/Solutions/products/workstations/nvidia-rtx-4000-sff-datasheet", "u": "https://www.nvidia.com/content/dam/en-zz/Solutions/products/workstations/nvidia-rtx-4000-sff-datasheet.pdf" }, { "t": "nvidia.com — /en-us/products/workstations/rtx-4000-sff/", "u": "https://www.nvidia.com/en-us/products/workstations/rtx-4000-sff/" }, { "t": "techpowerup.com — /gpu-specs/rtx-4000-sff-ada-generation.c4139", "u": "https://www.techpowerup.com/gpu-specs/rtx-4000-sff-ada-generation.c4139" } ], "aka": null }, { "id": "rtx-6000-ada", "name": "NVIDIA RTX 6000 Ada Generation", "short": "RTX 6000 Ada", "seg": "workstation", "arch": "Ada", "archGroup": "Ada", "cls": "ada-pro", "clsLabel": "Ada (RTX Ada, L4, L40S)", "chip": "AD102", "date": "2022-09", "t": 2022.6666666666667, "status": null, "ff": "4.4\" H x 10.5\" L, dual slot, full height", "mem": 48.0, "memType": "GDDR6", "bw": 960.0, "tdp": 300.0, "sms": 142.0, "tc": 568.0, "cuda": 18176.0, "boost": 2505.0, "v": { "fp32": [ 91.1, null, "p" ], "fp64": [ 1.4234, null, "d" ], "tf32": [ 182.1, 364.2, "p" ], "fp16": [ 364.0, 728.0, "p" ], "bf16": [ 364.0, 728.0, "p" ], "fp8": [ 728.5, 1457.0, "p" ], "int8": [ 728.5, 1457.0, "p" ], "int4": [ 1456.0, 2912.0, "d" ] }, "how": { "fp32": "NVIDIA: “Single-precision performance 91.1 TFLOPS³ | 3 Peak rates based on GPU Boost Clock.” [dam-cdn.nvd.orangelogic.com]", "fp64": "Derived: FP32 ÷ 64 (this architecture's FP64 rate)", "tf32": "NVIDIA: “Table 4: Peak TF32 Tensor TFLOPS¹ 182.1/364.2²” [nvidia.com]", "fp16": "NVIDIA: “Table 4: Peak FP16 Tensor TFLOPS with FP32 Accumulate¹ 364/728²” [nvidia.com]", "bf16": "NVIDIA: “Table 4: Peak BF16 Tensor TFLOPS with FP32 Accumulate¹ 364/728²” [nvidia.com]", "fp8": "NVIDIA: “Table 4: Peak FP8 Tensor TFLOPS with FP32 Accumulate¹ 728.5/1457²” [nvidia.com]", "int8": "NVIDIA: “Table 4: Peak INT8 Tensor TOPS¹ 728.5/1457.0²” [nvidia.com]", "int4": "Derived from NVIDIA's published FP16 figure of 364 dense. On workstation and data-centre Ada, INT4 runs at 4× the FP16 rate" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "fp6": "No FP6 tensor cores before Blackwell", "fp4": "No FP4 tensor cores before Blackwell" }, "headline": "“Tensor performance 1457.0 TFLOPS⁴ | 4 Effective FP8 teraFLOPS (TFLOPS) using the new sparsity feature.” — read as FP8, sparse", "anchor": "Derived from NVIDIA's published FP16 figure of 364 dense. ", "notes": "RTX PRO Blackwell whitepaper (v1.1) Table 4 gives the full NVIDIA precision breakdown for this card; the Ada architecture whitepaper (v2.02) has no workstation-card table.; Datasheet (Feb23, doc 2647623) via NVIDIA datasheet briefcase. Product page states the same figure in 'AI TOPS'.; RTX PRO whitepaper Table 1 lists RTX 6000 Ada bandwidth as 1008 GB/sec; its Table 4 and the datasheet say 960 GB/s (20 Gbps x 384-bit).", "sources": [ { "t": "dam-cdn.nvd.orangelogic.com — /AssetLink/83uo5f1t66fkm0dh16mi5uq1412l7ux5.pdf", "u": "https://dam-cdn.nvd.orangelogic.com/AssetLink/83uo5f1t66fkm0dh16mi5uq1412l7ux5.pdf" }, { "t": "resources.nvidia.com — /en-us-briefcase-for-datasheets/proviz-print-rtx6000-1", "u": "https://resources.nvidia.com/en-us-briefcase-for-datasheets/proviz-print-rtx6000-1" }, { "t": "nvidia.com — /en-us/products/workstations/rtx-6000/", "u": "https://www.nvidia.com/en-us/products/workstations/rtx-6000/" }, { "t": "nvidia.com — /content/dam/en-zz/Solutions/design-visualization/quadro-product-literature/pdf/", "u": "https://www.nvidia.com/content/dam/en-zz/Solutions/design-visualization/quadro-product-literature/pdf/NVIDIA-RTX-Blackwell-PRO-GPU-Architecture-v1_1.pdf" }, { "t": "techpowerup.com — /gpu-specs/rtx-6000-ada-generation.c3933", "u": "https://www.techpowerup.com/gpu-specs/rtx-6000-ada-generation.c3933" }, { "t": "globenewswire.com — /news-release/2022/09/20/2519485/0/en/NVIDIA-s-New-Ada-Lovelace-RTX-GPU-Arrives-", "u": "https://www.globenewswire.com/news-release/2022/09/20/2519485/0/en/NVIDIA-s-New-Ada-Lovelace-RTX-GPU-Arrives-for-Designers-and-Creators.html" } ], "aka": null }, { "id": "rtx-a5500", "name": "NVIDIA RTX A5500", "short": "RTX A5500", "seg": "workstation", "arch": "Ampere", "archGroup": "Ampere", "cls": "ampere-pro", "clsLabel": "Ampere GA10x (RTX A, A10, A40)", "chip": "GA102", "date": "2022-03", "t": 2022.1666666666667, "status": null, "ff": "4.4\" H x 10.5\" L, dual slot, full height", "mem": 24.0, "memType": "GDDR6", "bw": 768.0, "tdp": 230.0, "sms": null, "tc": 320.0, "cuda": 10240.0, "boost": 1665.0, "v": { "fp32": [ 34.1, null, "p" ], "fp64": [ 0.5328, null, "d" ], "tf32": [ 68.2, 136.4, "d" ], "fp16": [ 136.4, 272.8, "p" ], "bf16": [ 136.4, 272.8, "d" ], "int8": [ 272.8, 545.6, "d" ], "int4": [ 545.6, 1091.2, "d" ] }, "how": { "fp32": "NVIDIA: “Single-precision performance 34.1 TFLOPS⁵ | 5 Peak rates based on GPU Boost Clock.” [nvidia.com]", "fp64": "Derived: FP32 ÷ 64 (this architecture's FP64 rate)", "tf32": "Derived from NVIDIA's headline figure, 272.8 TFLOPS FP16 with sparsity (so 136.4 dense). On workstation and data-centre Ampere, TF32 runs at half the FP16 rate", "fp16": "NVIDIA: “Tensor performance 272.8 TFLOPS⁶ | 6 Effective teraFLOPS (TFLOPS) using the new sparsity feature.” (precision not stated; workstation and data-centre Ampere headline figures are FP16) (dense = half the sparse figure) [nvidia.com]", "bf16": "Derived from NVIDIA's headline figure, 272.8 TFLOPS FP16 with sparsity (so 136.4 dense). On workstation and data-centre Ampere, BF16 runs at the same rate as FP16", "int8": "Derived from NVIDIA's headline figure, 272.8 TFLOPS FP16 with sparsity (so 136.4 dense). On workstation and data-centre Ampere, INT8 runs at twice the FP16 rate", "int4": "Derived from NVIDIA's headline figure, 272.8 TFLOPS FP16 with sparsity (so 136.4 dense). On workstation and data-centre Ampere, INT4 runs at 4× the FP16 rate" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "fp8": "No FP8 tensor cores before Ada/Hopper (FP8 models run at FP16 speed)", "fp6": "No FP6 tensor cores before Blackwell", "fp4": "No FP4 tensor cores before Blackwell" }, "headline": "“Tensor performance 272.8 TFLOPS⁶ | 6 Effective teraFLOPS (TFLOPS) using the new sparsity feature.”", "anchor": "Derived from NVIDIA's headline figure, 272.8 TFLOPS FP16 with sparsity (so 136.4 dense). ", "notes": "Datasheet dated MAR22.", "sources": [ { "t": "nvidia.com — /content/dam/en-zz/Solutions/products/workstations/nvidia-rtx-a5500-datasheet.pd", "u": "https://www.nvidia.com/content/dam/en-zz/Solutions/products/workstations/nvidia-rtx-a5500-datasheet.pdf" }, { "t": "nvidia.com — /en-us/products/workstations/rtx-a5500/", "u": "https://www.nvidia.com/en-us/products/workstations/rtx-a5500/" }, { "t": "techpowerup.com — /gpu-specs/rtx-a5500.c3901", "u": "https://www.techpowerup.com/gpu-specs/rtx-a5500.c3901" } ], "aka": null }, { "id": "rtx-a2000-12gb", "name": "NVIDIA RTX A2000 12GB", "short": "RTX A2000 12GB", "seg": "workstation", "arch": "Ampere", "archGroup": "Ampere", "cls": "ampere-pro", "clsLabel": "Ampere GA10x (RTX A, A10, A40)", "chip": "GA106", "date": "2021-11", "t": 2021.8333333333333, "status": null, "ff": "2.7\" H x 6.6\" L, dual slot", "mem": 12.0, "memType": "GDDR6", "bw": 288.0, "tdp": 70.0, "sms": null, "tc": 104.0, "cuda": 3328.0, "boost": 1200.0, "v": { "fp32": [ 8.0, null, "p" ], "fp64": [ 0.125, null, "d" ], "tf32": [ 15.975, 31.95, "d" ], "fp16": [ 31.95, 63.9, "p" ], "bf16": [ 31.95, 63.9, "d" ], "int8": [ 63.9, 127.8, "d" ], "int4": [ 127.8, 255.6, "d" ] }, "how": { "fp32": "NVIDIA: “Single-precision performance 8.0 TFLOPS² | 2 Peak rates based on GPU Boost Clock.” [nvidia.com]", "fp64": "Derived: FP32 ÷ 64 (this architecture's FP64 rate)", "tf32": "Derived from NVIDIA's headline figure, 63.9 TFLOPS FP16 with sparsity (so 31.95 dense). On workstation and data-centre Ampere, TF32 runs at half the FP16 rate", "fp16": "NVIDIA: “Tensor performance 63.9 TFLOPS³ | 3 Effective teraFLOPS (TFLOPS) using the new sparsity feature.” (precision not stated; workstation and data-centre Ampere headline figures are FP16) (dense = half the sparse figure) [nvidia.com]", "bf16": "Derived from NVIDIA's headline figure, 63.9 TFLOPS FP16 with sparsity (so 31.95 dense). On workstation and data-centre Ampere, BF16 runs at the same rate as FP16", "int8": "Derived from NVIDIA's headline figure, 63.9 TFLOPS FP16 with sparsity (so 31.95 dense). On workstation and data-centre Ampere, INT8 runs at twice the FP16 rate", "int4": "Derived from NVIDIA's headline figure, 63.9 TFLOPS FP16 with sparsity (so 31.95 dense). On workstation and data-centre Ampere, INT4 runs at 4× the FP16 rate" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "fp8": "No FP8 tensor cores before Ada/Hopper (FP8 models run at FP16 speed)", "fp6": "No FP6 tensor cores before Blackwell", "fp4": "No FP4 tensor cores before Blackwell" }, "headline": "“Tensor performance 63.9 TFLOPS³ | 3 Effective teraFLOPS (TFLOPS) using the new sparsity feature.”", "anchor": "Derived from NVIDIA's headline figure, 63.9 TFLOPS FP16 with sparsity (so 31.95 dense). ", "notes": "Same datasheet as RTX A2000 (6GB); only memory differs (12GB GDDR6).", "sources": [ { "t": "nvidia.com — /content/dam/en-zz/Solutions/products/workstations/nvidia-rtx-a2000-12gb-datashe", "u": "https://www.nvidia.com/content/dam/en-zz/Solutions/products/workstations/nvidia-rtx-a2000-12gb-datasheet.pdf" }, { "t": "nvidia.com — /en-us/products/workstations/rtx-a2000/", "u": "https://www.nvidia.com/en-us/products/workstations/rtx-a2000/" }, { "t": "techpowerup.com — /gpu-specs/rtx-a2000-12-gb.c3853", "u": "https://www.techpowerup.com/gpu-specs/rtx-a2000-12-gb.c3853" } ], "aka": null }, { "id": "rtx-a4500", "name": "NVIDIA RTX A4500", "short": "RTX A4500", "seg": "workstation", "arch": "Ampere", "archGroup": "Ampere", "cls": "ampere-pro", "clsLabel": "Ampere GA10x (RTX A, A10, A40)", "chip": "GA102", "date": "2021-11", "t": 2021.8333333333333, "status": null, "ff": "4.4\" H x 10.5\" L, dual slot, full height", "mem": 20.0, "memType": "GDDR6", "bw": 640.0, "tdp": 200.0, "sms": null, "tc": 224.0, "cuda": 7168.0, "boost": 1650.0, "v": { "fp32": [ 23.7, null, "p" ], "fp64": [ 0.3703, null, "d" ], "tf32": [ 47.3, 94.6, "d" ], "fp16": [ 94.6, 189.2, "p" ], "bf16": [ 94.6, 189.2, "d" ], "int8": [ 189.2, 378.4, "d" ], "int4": [ 378.4, 756.8, "d" ] }, "how": { "fp32": "NVIDIA: “Single-precision performance 23.7 TFLOPS⁵ | 5 Peak rates based on GPU Boost Clock.” [nvidia.com]", "fp64": "Derived: FP32 ÷ 64 (this architecture's FP64 rate)", "tf32": "Derived from NVIDIA's headline figure, 189.2 TFLOPS FP16 with sparsity (so 94.6 dense). On workstation and data-centre Ampere, TF32 runs at half the FP16 rate", "fp16": "NVIDIA: “Tensor performance 189.2 TFLOPS⁶ | 6 Effective teraFLOPS (TFLOPS) using the new sparsity feature.” (precision not stated; workstation and data-centre Ampere headline figures are FP16) (dense = half the sparse figure) [nvidia.com]", "bf16": "Derived from NVIDIA's headline figure, 189.2 TFLOPS FP16 with sparsity (so 94.6 dense). On workstation and data-centre Ampere, BF16 runs at the same rate as FP16", "int8": "Derived from NVIDIA's headline figure, 189.2 TFLOPS FP16 with sparsity (so 94.6 dense). On workstation and data-centre Ampere, INT8 runs at twice the FP16 rate", "int4": "Derived from NVIDIA's headline figure, 189.2 TFLOPS FP16 with sparsity (so 94.6 dense). On workstation and data-centre Ampere, INT4 runs at 4× the FP16 rate" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "fp8": "No FP8 tensor cores before Ada/Hopper (FP8 models run at FP16 speed)", "fp6": "No FP6 tensor cores before Blackwell", "fp4": "No FP4 tensor cores before Blackwell" }, "headline": "“Tensor performance 189.2 TFLOPS⁶ | 6 Effective teraFLOPS (TFLOPS) using the new sparsity feature.”", "anchor": "Derived from NVIDIA's headline figure, 189.2 TFLOPS FP16 with sparsity (so 94.6 dense). ", "notes": "Datasheet dated FEB23 (doc 2564322). NVLink bandwidth 112.5 GB/s (bidirectional).", "sources": [ { "t": "nvidia.com — /content/dam/en-zz/Solutions/products/workstations/nvidia-rtx-a4500-datasheet.pd", "u": "https://www.nvidia.com/content/dam/en-zz/Solutions/products/workstations/nvidia-rtx-a4500-datasheet.pdf" }, { "t": "nvidia.com — /en-us/products/workstations/rtx-a4500/", "u": "https://www.nvidia.com/en-us/products/workstations/rtx-a4500/" }, { "t": "techpowerup.com — /gpu-specs/rtx-a4500.c3849", "u": "https://www.techpowerup.com/gpu-specs/rtx-a4500.c3849" } ], "aka": null }, { "id": "rtx-a2000", "name": "NVIDIA RTX A2000", "short": "RTX A2000", "seg": "workstation", "arch": "Ampere", "archGroup": "Ampere", "cls": "ampere-pro", "clsLabel": "Ampere GA10x (RTX A, A10, A40)", "chip": "GA106", "date": "2021-08", "t": 2021.5833333333333, "status": null, "ff": "2.7\" H x 6.6\" L, dual slot", "mem": 6.0, "memType": "GDDR6", "bw": 288.0, "tdp": 70.0, "sms": null, "tc": 104.0, "cuda": 3328.0, "boost": 1200.0, "v": { "fp32": [ 8.0, null, "p" ], "fp64": [ 0.125, null, "d" ], "tf32": [ 15.975, 31.95, "d" ], "fp16": [ 31.95, 63.9, "p" ], "bf16": [ 31.95, 63.9, "d" ], "int8": [ 63.9, 127.8, "d" ], "int4": [ 127.8, 255.6, "d" ] }, "how": { "fp32": "NVIDIA: “Single-precision performance 8.0 TFLOPS² | 2 Peak rates based on GPU Boost Clock.” [nvidia.com]", "fp64": "Derived: FP32 ÷ 64 (this architecture's FP64 rate)", "tf32": "Derived from NVIDIA's headline figure, 63.9 TFLOPS FP16 with sparsity (so 31.95 dense). On workstation and data-centre Ampere, TF32 runs at half the FP16 rate", "fp16": "NVIDIA: “Tensor performance 63.9 TFLOPS³ | 3 Effective teraFLOPS (TFLOPS) using the new sparsity feature.” (precision not stated; workstation and data-centre Ampere headline figures are FP16) (dense = half the sparse figure) [nvidia.com]", "bf16": "Derived from NVIDIA's headline figure, 63.9 TFLOPS FP16 with sparsity (so 31.95 dense). On workstation and data-centre Ampere, BF16 runs at the same rate as FP16", "int8": "Derived from NVIDIA's headline figure, 63.9 TFLOPS FP16 with sparsity (so 31.95 dense). On workstation and data-centre Ampere, INT8 runs at twice the FP16 rate", "int4": "Derived from NVIDIA's headline figure, 63.9 TFLOPS FP16 with sparsity (so 31.95 dense). On workstation and data-centre Ampere, INT4 runs at 4× the FP16 rate" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "fp8": "No FP8 tensor cores before Ada/Hopper (FP8 models run at FP16 speed)", "fp6": "No FP6 tensor cores before Blackwell", "fp4": "No FP4 tensor cores before Blackwell" }, "headline": "“Tensor performance 63.9 TFLOPS³ | 3 Effective teraFLOPS (TFLOPS) using the new sparsity feature.”", "anchor": "Derived from NVIDIA's headline figure, 63.9 TFLOPS FP16 with sparsity (so 31.95 dense). ", "notes": "Single NVIDIA datasheet (MAY22) covers both RTX A2000 (6GB) and RTX A2000 12GB with identical throughput.; NVIDIA product pages for A2000 show no throughput figures; datasheet only.", "sources": [ { "t": "nvidia.com — /content/dam/en-zz/Solutions/products/workstations/nvidia-rtx-a2000-12gb-datashe", "u": "https://www.nvidia.com/content/dam/en-zz/Solutions/products/workstations/nvidia-rtx-a2000-12gb-datasheet.pdf" }, { "t": "nvidia.com — /en-us/products/workstations/rtx-a2000/", "u": "https://www.nvidia.com/en-us/products/workstations/rtx-a2000/" }, { "t": "techpowerup.com — /gpu-specs/rtx-a2000.c3820", "u": "https://www.techpowerup.com/gpu-specs/rtx-a2000.c3820" }, { "t": "anandtech.com — /show/16875", "u": "https://anandtech.com/show/16875" } ], "aka": null }, { "id": "rtx-a4000", "name": "NVIDIA RTX A4000", "short": "RTX A4000", "seg": "workstation", "arch": "Ampere", "archGroup": "Ampere", "cls": "ampere-pro", "clsLabel": "Ampere GA10x (RTX A, A10, A40)", "chip": "GA104", "date": "2021-04", "t": 2021.25, "status": null, "ff": "4.4\" H x 9.5\" L, single slot", "mem": 16.0, "memType": "GDDR6", "bw": 448.0, "tdp": 140.0, "sms": null, "tc": 192.0, "cuda": 6144.0, "boost": 1560.0, "v": { "fp32": [ 19.2, null, "p" ], "fp64": [ 0.3, null, "d" ], "tf32": [ 38.35, 76.7, "d" ], "fp16": [ 76.7, 153.4, "p" ], "bf16": [ 76.7, 153.4, "d" ], "int8": [ 153.4, 306.8, "d" ], "int4": [ 306.8, 613.6, "d" ] }, "how": { "fp32": "NVIDIA: “Single-precision performance 19.2 TFLOPS³ | 3 Peak rates based on GPU Boost Clock.” [nvidia.com]", "fp64": "Derived: FP32 ÷ 64 (this architecture's FP64 rate)", "tf32": "Derived from NVIDIA's headline figure, 153.4 TFLOPS FP16 with sparsity (so 76.7 dense). On workstation and data-centre Ampere, TF32 runs at half the FP16 rate", "fp16": "NVIDIA: “Tensor performance 153.4 TFLOPS⁴ | 4 Effective teraFLOPS (TFLOPS) using the new sparsity feature.” (precision not stated; workstation and data-centre Ampere headline figures are FP16) (dense = half the sparse figure) [nvidia.com]", "bf16": "Derived from NVIDIA's headline figure, 153.4 TFLOPS FP16 with sparsity (so 76.7 dense). On workstation and data-centre Ampere, BF16 runs at the same rate as FP16", "int8": "Derived from NVIDIA's headline figure, 153.4 TFLOPS FP16 with sparsity (so 76.7 dense). On workstation and data-centre Ampere, INT8 runs at twice the FP16 rate", "int4": "Derived from NVIDIA's headline figure, 153.4 TFLOPS FP16 with sparsity (so 76.7 dense). On workstation and data-centre Ampere, INT4 runs at 4× the FP16 rate" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "fp8": "No FP8 tensor cores before Ada/Hopper (FP8 models run at FP16 speed)", "fp6": "No FP6 tensor cores before Blackwell", "fp4": "No FP4 tensor cores before Blackwell" }, "headline": "“Tensor performance 153.4 TFLOPS⁴ | 4 Effective teraFLOPS (TFLOPS) using the new sparsity feature.”", "anchor": "Derived from NVIDIA's headline figure, 153.4 TFLOPS FP16 with sparsity (so 76.7 dense). ", "notes": "Datasheet PDF (MAY22) is a scanned/OCR'd document; values confirmed from the rendered page image.", "sources": [ { "t": "nvidia.com — /content/dam/en-zz/Solutions/products/workstations/nvidia-rtx-a4000-datasheet.pd", "u": "https://www.nvidia.com/content/dam/en-zz/Solutions/products/workstations/nvidia-rtx-a4000-datasheet.pdf" }, { "t": "nvidia.com — /en-us/products/workstations/rtx-a4000/", "u": "https://www.nvidia.com/en-us/products/workstations/rtx-a4000/" }, { "t": "techpowerup.com — /gpu-specs/rtx-a4000.c3756", "u": "https://www.techpowerup.com/gpu-specs/rtx-a4000.c3756" } ], "aka": null, "measured": { "best": { "fp32": { "value": 12.44, "unit": "TFLOPS", "sm_mhz": 1282.0, "power_w": 109.2 }, "tf32": { "value": 31.35, "unit": "TFLOPS", "sm_mhz": 1320.0, "power_w": 139.8 }, "fp16": { "value": 61.81, "unit": "TFLOPS", "sm_mhz": 1290.0, "power_w": 130.8 }, "fp16_acc16": { "value": 62.91, "unit": "TFLOPS", "sm_mhz": 1320.0, "power_w": 139.8 }, "bf16": { "value": 62.33, "unit": "TFLOPS", "sm_mhz": 1275.0, "power_w": 139.8 }, "int8": { "value": 116.94, "unit": "TOPS", "sm_mhz": 1268.0, "power_w": 139.7 }, "fp64": { "value": 0.32, "unit": "TFLOPS", "sm_mhz": 1950.0, "power_w": 102.6 }, "dram": { "value": 390.97, "unit": "GB/s", "sm_mhz": 1845.0, "power_w": 128.5 } } } }, { "id": "rtx-a5000", "name": "NVIDIA RTX A5000", "short": "RTX A5000", "seg": "workstation", "arch": "Ampere", "archGroup": "Ampere", "cls": "ampere-pro", "clsLabel": "Ampere GA10x (RTX A, A10, A40)", "chip": "GA102", "date": "2021-04", "t": 2021.25, "status": null, "ff": "4.4\" H x 10.5\" L, dual slot, full height", "mem": 24.0, "memType": "GDDR6", "bw": 768.0, "tdp": 230.0, "sms": null, "tc": 256.0, "cuda": 8192.0, "boost": 1695.0, "v": { "fp32": [ 27.8, null, "p" ], "fp64": [ 0.4344, null, "d" ], "tf32": [ 55.55, 111.1, "d" ], "fp16": [ 111.1, 222.2, "p" ], "bf16": [ 111.1, 222.2, "d" ], "int8": [ 222.2, 444.4, "d" ], "int4": [ 444.4, 888.8, "d" ] }, "how": { "fp32": "NVIDIA: “Single-precision performance 27.8 TFLOPS⁵ | 5 Peak rates based on GPU Boost Clock.” [nvidia.com]", "fp64": "Derived: FP32 ÷ 64 (this architecture's FP64 rate)", "tf32": "Derived from NVIDIA's headline figure, 222.2 TFLOPS FP16 with sparsity (so 111.1 dense). On workstation and data-centre Ampere, TF32 runs at half the FP16 rate", "fp16": "NVIDIA: “Tensor performance 222.2 TFLOPS⁶ | 6 Effective teraFLOPS (TFLOPS) using the new sparsity feature.” (precision not stated; workstation and data-centre Ampere headline figures are FP16) (dense = half the sparse figure) [nvidia.com]", "bf16": "Derived from NVIDIA's headline figure, 222.2 TFLOPS FP16 with sparsity (so 111.1 dense). On workstation and data-centre Ampere, BF16 runs at the same rate as FP16", "int8": "Derived from NVIDIA's headline figure, 222.2 TFLOPS FP16 with sparsity (so 111.1 dense). On workstation and data-centre Ampere, INT8 runs at twice the FP16 rate", "int4": "Derived from NVIDIA's headline figure, 222.2 TFLOPS FP16 with sparsity (so 111.1 dense). On workstation and data-centre Ampere, INT4 runs at 4× the FP16 rate" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "fp8": "No FP8 tensor cores before Ada/Hopper (FP8 models run at FP16 speed)", "fp6": "No FP6 tensor cores before Blackwell", "fp4": "No FP4 tensor cores before Blackwell" }, "headline": "“Tensor performance 222.2 TFLOPS⁶ | 6 Effective teraFLOPS (TFLOPS) using the new sparsity feature.”", "anchor": "Derived from NVIDIA's headline figure, 222.2 TFLOPS FP16 with sparsity (so 111.1 dense). ", "notes": "Datasheet dated MAY22.", "sources": [ { "t": "nvidia.com — /content/dam/en-zz/Solutions/products/workstations/nvidia-rtx-a5000-datasheet.pd", "u": "https://www.nvidia.com/content/dam/en-zz/Solutions/products/workstations/nvidia-rtx-a5000-datasheet.pdf" }, { "t": "nvidia.com — /en-us/products/workstations/rtx-a5000/", "u": "https://www.nvidia.com/en-us/products/workstations/rtx-a5000/" }, { "t": "techpowerup.com — /gpu-specs/rtx-a5000.c3748", "u": "https://www.techpowerup.com/gpu-specs/rtx-a5000.c3748" } ], "aka": null, "measured": { "best": { "fp32": { "value": 17.32, "unit": "TFLOPS", "sm_mhz": 1327.5, "power_w": 154.76999999999998 }, "tf32": { "value": 44.57, "unit": "TFLOPS", "sm_mhz": 1395.0, "power_w": 227.47 }, "fp16": { "value": 88.33, "unit": "TFLOPS", "sm_mhz": 1380.0, "power_w": 213.13 }, "fp16_acc16": { "value": 88.76, "unit": "TFLOPS", "sm_mhz": 1395.0, "power_w": 229.2 }, "bf16": { "value": 90.62, "unit": "TFLOPS", "sm_mhz": 1417.5, "power_w": 222.46 }, "int8": { "value": 166.62, "unit": "TOPS", "sm_mhz": 1365.0, "power_w": 228.64 }, "fp64": { "value": 0.42, "unit": "TFLOPS", "sm_mhz": 1890.0, "power_w": 137.51 }, "dram": { "value": 683.98, "unit": "GB/s", "sm_mhz": 1785.0, "power_w": 198.45999999999998 } } } }, { "id": "rtx-a6000", "name": "NVIDIA RTX A6000", "short": "RTX A6000", "seg": "workstation", "arch": "Ampere", "archGroup": "Ampere", "cls": "ampere-pro", "clsLabel": "Ampere GA10x (RTX A, A10, A40)", "chip": "GA102", "date": "2020-10", "t": 2020.75, "status": null, "ff": "4.4\" H x 10.5\" L, dual slot, full height", "mem": 48.0, "memType": "GDDR6", "bw": 768.0, "tdp": 300.0, "sms": 84.0, "tc": 336.0, "cuda": 10752.0, "boost": 1800.0, "v": { "fp32": [ 38.7, null, "p" ], "fp64": [ 0.6047, null, "d" ], "tf32": [ 77.4, 154.8, "p" ], "fp16": [ 154.8, 309.6, "p" ], "bf16": [ 154.8, 309.6, "p" ], "int8": [ 309.7, 619.4, "p" ], "int4": [ 619.3, 1238.6, "p" ] }, "how": { "fp32": "NVIDIA: “Table 3, NVIDIA RTX A6000: Peak FP32 TFLOPS (non-Tensor)¹ 38.7 | 1. Peak rates are based on GPU Boost Clock.” [nvidia.com]", "fp64": "Derived: FP32 ÷ 64 (this architecture's FP64 rate)", "tf32": "NVIDIA: “Table 3: Peak TF32 Tensor TFLOPS¹ 77.4/154.8²” [nvidia.com]", "fp16": "NVIDIA: “Table 3: Peak FP16 Tensor TFLOPS with FP32 Accumulate¹ 154.8/309.6²” [nvidia.com]", "bf16": "NVIDIA: “Table 3: Peak BF16 Tensor TFLOPS with FP32 Accumulate¹ 154.8/309.6²” [nvidia.com]", "int8": "NVIDIA: “Table 3: Peak INT8 Tensor TOPS¹ 309.7/619.4²” [nvidia.com]", "int4": "NVIDIA: “Table 3: Peak INT4 Tensor TOPS¹ 619.3/1238.6²” [nvidia.com]" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "fp8": "No FP8 tensor cores before Ada/Hopper (FP8 models run at FP16 speed)", "fp6": "No FP6 tensor cores before Blackwell", "fp4": "No FP4 tensor cores before Blackwell" }, "headline": "“Tensor performance 309.7 TFLOPS⁸ | 8 Effective teraFLOPS (TFLOPS) using the new sparsity feature.” — read as FP16, sparse", "anchor": "Derived from NVIDIA's published FP16 figure of 154.8 dense. ", "notes": "RTX PRO Blackwell whitepaper Table 4 repeats the same A6000 tensor figures (no INT4 row) and RT 76 TFLOPS (datasheet 75.6).; RTX PRO Blackwell whitepaper Table 1 wrongly lists A6000 memory as 19.5 Gbps / 936 GB/sec; its Table 4 says 768 GB/sec (still with 19.5 Gbps); GA102 whitepaper and datasheet say 16 Gbps / 768 GB/s.; Datasheet dated MAY22.", "sources": [ { "t": "nvidia.com — /content/dam/en-zz/Solutions/products/workstations/nvidia-rtx-a6000-datasheet.pd", "u": "https://www.nvidia.com/content/dam/en-zz/Solutions/products/workstations/nvidia-rtx-a6000-datasheet.pdf" }, { "t": "nvidia.com — /content/PDF/nvidia-ampere-ga-102-gpu-architecture-whitepaper-v2.pdf", "u": "https://www.nvidia.com/content/PDF/nvidia-ampere-ga-102-gpu-architecture-whitepaper-v2.pdf" }, { "t": "nvidia.com — /content/dam/en-zz/Solutions/design-visualization/quadro-product-literature/pdf/", "u": "https://www.nvidia.com/content/dam/en-zz/Solutions/design-visualization/quadro-product-literature/pdf/NVIDIA-RTX-Blackwell-PRO-GPU-Architecture-v1_1.pdf" }, { "t": "nvidia.com — /en-us/products/workstations/rtx-a6000/", "u": "https://www.nvidia.com/en-us/products/workstations/rtx-a6000/" }, { "t": "techpowerup.com — /gpu-specs/rtx-a6000.c3686", "u": "https://www.techpowerup.com/gpu-specs/rtx-a6000.c3686" } ], "aka": null }, { "id": "quadro-rtx-4000", "name": "NVIDIA Quadro RTX 4000", "short": "Quadro RTX 4000", "seg": "workstation", "arch": "Turing", "archGroup": "Turing", "cls": "turing-pro", "clsLabel": "Turing (Quadro, Tesla, TITAN)", "chip": "TU104", "date": "2018-11", "t": 2018.8333333333333, "status": null, "ff": "4.4\" H x 9.5\" L, single slot", "mem": 8.0, "memType": "GDDR6", "bw": 416.0, "tdp": 160.0, "sms": null, "tc": 288.0, "cuda": 2304.0, "boost": 1545.0, "v": { "fp32": [ 7.1, null, "p" ], "fp64": [ 0.2219, null, "d" ], "fp16": [ 57.0, null, "p" ], "int8": [ 114.0, null, "d" ], "int4": [ 228.0, null, "d" ] }, "how": { "fp32": "NVIDIA: “Single-Precision 7.1 TFLOPS” [nvidia.com]", "fp64": "Derived: FP32 ÷ 32 (this architecture's FP64 rate)", "fp16": "NVIDIA: “Tensor Performance 57.0 TFLOPS (no footnote on this row)” (precision not stated; Turing workstation and data-centre cards headline figures are FP16) [nvidia.com]", "int8": "Derived from NVIDIA's headline figure, 57 TFLOPS FP16. On Turing workstation and data-centre cards, INT8 runs at twice the FP16 rate", "int4": "Derived from NVIDIA's headline figure, 57 TFLOPS FP16. On Turing workstation and data-centre cards, INT4 runs at 4× the FP16 rate" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "tf32": "TF32 tensor cores arrived with Ampere", "bf16": "BF16 tensor cores arrived with Ampere", "fp8": "No FP8 tensor cores before Ada/Hopper (FP8 models run at FP16 speed)", "fp6": "No FP6 tensor cores before Blackwell", "fp4": "No FP4 tensor cores before Blackwell" }, "headline": "“Tensor Performance 57.0 TFLOPS (no footnote on this row)”", "anchor": "Derived from NVIDIA's headline figure, 57 TFLOPS FP16. ", "notes": "Datasheet (APRIL19) gives Tensor Performance 57.0 TFLOPS with no precision note.; Leadtek also lists '28.5 TOPS of integer-precision (INT8)' (non-tensor DP4A-style figure); not recorded.; ECC not listed on the datasheet.", "sources": [ { "t": "nvidia.com — /content/dam/en-zz/Solutions/design-visualization/quadro-product-literature/quad", "u": "https://www.nvidia.com/content/dam/en-zz/Solutions/design-visualization/quadro-product-literature/quadro-rtx-4000-data-sheet-us-nvidia-830682-r6-web.pdf" }, { "t": "web.archive.org — /web/20190705221914/https://www.nvidia.com/en-us/design-visualization/quadro/rtx", "u": "https://web.archive.org/web/20190705221914/https://www.nvidia.com/en-us/design-visualization/quadro/rtx-4000/" }, { "t": "leadtek.com — /eng/products/workstation_graphics(2)/NVIDIA_Quadro_RTX4000(10827)/detail", "u": "https://www.leadtek.com/eng/products/workstation_graphics(2)/NVIDIA_Quadro_RTX4000(10827)/detail" }, { "t": "techpowerup.com — /gpu-specs/quadro-rtx-4000.c3336", "u": "https://www.techpowerup.com/gpu-specs/quadro-rtx-4000.c3336" }, { "t": "cgchannel.com — /2018/11/nvidia-announces-900-quadro-rtx-4000-gpu", "u": "https://www.cgchannel.com/2018/11/nvidia-announces-900-quadro-rtx-4000-gpu" } ], "aka": null }, { "id": "quadro-rtx-5000", "name": "NVIDIA Quadro RTX 5000", "short": "Quadro RTX 5000", "seg": "workstation", "arch": "Turing", "archGroup": "Turing", "cls": "turing-pro", "clsLabel": "Turing (Quadro, Tesla, TITAN)", "chip": "TU104", "date": "2018-08", "t": 2018.5833333333333, "status": null, "ff": "4.4\" H x 10.5\" L, dual slot, full height", "mem": 16.0, "memType": "GDDR6", "bw": 448.0, "tdp": 265.0, "sms": 48.0, "tc": 384.0, "cuda": 3072.0, "boost": 1815.0, "v": { "fp32": [ 11.2, null, "p" ], "fp64": [ 0.35, null, "d" ], "fp16": [ 89.2, null, "p" ], "int8": [ 178.4, null, "p" ], "int4": [ 356.8, null, "p" ] }, "how": { "fp32": "NVIDIA: “Table 4, Quadro RTX 5000: Peak FP32 TFLOPS* 11.2 (* Peak TFLOPS and TOPS rates are based on GPU Boost Clock.)” [images.nvidia.com]", "fp64": "Derived: FP32 ÷ 32 (this architecture's FP64 rate)", "fp16": "NVIDIA: “Table 4, Quadro RTX 5000: Peak FP16 Tensor TFLOPS with FP32 Accumulate* 89.2” [images.nvidia.com]", "int8": "NVIDIA: “Table 4, Quadro RTX 5000: Peak INT8 Tensor TOPS* 178.4” [images.nvidia.com]", "int4": "NVIDIA: “Table 4, Quadro RTX 5000: Peak INT4 Tensor TOPS* 356.8” [images.nvidia.com]" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "tf32": "TF32 tensor cores arrived with Ampere", "bf16": "BF16 tensor cores arrived with Ampere", "fp8": "No FP8 tensor cores before Ada/Hopper (FP8 models run at FP16 speed)", "fp6": "No FP6 tensor cores before Blackwell", "fp4": "No FP4 tensor cores before Blackwell" }, "headline": "“Tensor Performance 89.2 TFLOPS (datasheet; no footnote)” — read as FP16", "anchor": "Derived from NVIDIA's published FP16 figure of 89.2 dense. ", "notes": "Datasheet (Mar19): Single-Precision 11.2 TFLOPS, Tensor Performance 89.2 TFLOPS, no precision footnote; whitepaper Table 4 resolves it as FP16 tensor (FP16 and FP32 accumulate both 89.2), dense.; TechPowerUp also shows 1815 MHz (matches whitepaper).", "sources": [ { "t": "nvidia.com — /content/dam/en-zz/Solutions/design-visualization/quadro-product-literature/quad", "u": "https://www.nvidia.com/content/dam/en-zz/Solutions/design-visualization/quadro-product-literature/quadro-rtx-5000-data-sheet-us-nvidia-704120-r4-web.pdf" }, { "t": "images.nvidia.com — /aem-dam/en-zz/Solutions/design-visualization/technologies/turing-architecture/N", "u": "https://images.nvidia.com/aem-dam/en-zz/Solutions/design-visualization/technologies/turing-architecture/NVIDIA-Turing-Architecture-Whitepaper.pdf" }, { "t": "web.archive.org — /web/20200626200650/https://www.nvidia.com/en-us/design-visualization/quadro/rtx", "u": "https://web.archive.org/web/20200626200650/https://www.nvidia.com/en-us/design-visualization/quadro/rtx-5000/" }, { "t": "techpowerup.com — /gpu-specs/quadro-rtx-5000.c3308", "u": "https://www.techpowerup.com/gpu-specs/quadro-rtx-5000.c3308" } ], "aka": null }, { "id": "quadro-rtx-6000", "name": "NVIDIA Quadro RTX 6000", "short": "Quadro RTX 6000", "seg": "workstation", "arch": "Turing", "archGroup": "Turing", "cls": "turing-pro", "clsLabel": "Turing (Quadro, Tesla, TITAN)", "chip": "TU102", "date": "2018-08", "t": 2018.5833333333333, "status": null, "ff": "4.4\" H x 10.5\" L, dual slot, full height", "mem": 24.0, "memType": "GDDR6", "bw": 672.0, "tdp": 295.0, "sms": 72.0, "tc": 576.0, "cuda": 4608.0, "boost": 1770.0, "v": { "fp32": [ 16.3, null, "p" ], "fp64": [ 0.5094, null, "d" ], "fp16": [ 130.5, null, "p" ], "int8": [ 261.0, null, "p" ], "int4": [ 522.0, null, "p" ] }, "how": { "fp32": "NVIDIA: “Table 1, Quadro RTX 6000: Peak FP32 TFLOPS* 16.3 (* Peak TFLOPS, TIPS, and TOPS rates are based on GPU Boost Clock.)” [images.nvidia.com]", "fp64": "Derived: FP32 ÷ 32 (this architecture's FP64 rate)", "fp16": "NVIDIA: “Table 1, Quadro RTX 6000: Peak FP16 Tensor TFLOPS with FP32 Accumulate* 130.5” [images.nvidia.com]", "int8": "NVIDIA: “Table 1, Quadro RTX 6000: Peak INT8 Tensor TOPS* 261.0” [images.nvidia.com]", "int4": "NVIDIA: “Table 1, Quadro RTX 6000: Peak INT4 Tensor TOPS* 522.0” [images.nvidia.com]" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "tf32": "TF32 tensor cores arrived with Ampere", "bf16": "BF16 tensor cores arrived with Ampere", "fp8": "No FP8 tensor cores before Ada/Hopper (FP8 models run at FP16 speed)", "fp6": "No FP6 tensor cores before Blackwell", "fp4": "No FP4 tensor cores before Blackwell" }, "headline": "“Tensor Performance 130.5 TFLOPS (datasheet; no footnote)” — read as FP16", "anchor": "Derived from NVIDIA's published FP16 figure of 130.5 dense. ", "notes": "Datasheet (Mar19) has no tensor footnote; Turing whitepaper Table 1 gives the full precision breakdown (FP16 tensor 130.5 with FP16 or FP32 accumulate, INT8 261.0, INT4 522.0).; Passive (server) variant of Quadro RTX 6000 exists with lower clocks; excluded (not a desktop card).", "sources": [ { "t": "nvidia.com — /content/dam/en-zz/Solutions/design-visualization/quadro-product-literature/quad", "u": "https://www.nvidia.com/content/dam/en-zz/Solutions/design-visualization/quadro-product-literature/quadro-rtx-6000-us-nvidia-704093-r4-web.pdf" }, { "t": "images.nvidia.com — /aem-dam/en-zz/Solutions/design-visualization/technologies/turing-architecture/N", "u": "https://images.nvidia.com/aem-dam/en-zz/Solutions/design-visualization/technologies/turing-architecture/NVIDIA-Turing-Architecture-Whitepaper.pdf" }, { "t": "web.archive.org — /web/20200529112100/https://www.nvidia.com/en-us/design-visualization/quadro/rtx", "u": "https://web.archive.org/web/20200529112100/https://www.nvidia.com/en-us/design-visualization/quadro/rtx-6000/" }, { "t": "techpowerup.com — /gpu-specs/quadro-rtx-6000.c3307", "u": "https://www.techpowerup.com/gpu-specs/quadro-rtx-6000.c3307" } ], "aka": null }, { "id": "quadro-rtx-8000", "name": "NVIDIA Quadro RTX 8000", "short": "Quadro RTX 8000", "seg": "workstation", "arch": "Turing", "archGroup": "Turing", "cls": "turing-pro", "clsLabel": "Turing (Quadro, Tesla, TITAN)", "chip": "TU102", "date": "2018-08", "t": 2018.5833333333333, "status": null, "ff": "4.4\" H x 10.5\" L, dual slot, full height", "mem": 48.0, "memType": "GDDR6", "bw": 672.0, "tdp": 295.0, "sms": null, "tc": 576.0, "cuda": 4608.0, "boost": 1770.0, "v": { "fp32": [ 16.3, null, "p" ], "fp64": [ 0.5094, null, "d" ], "fp16": [ 130.5, null, "p" ], "int8": [ 261.0, null, "d" ], "int4": [ 522.0, null, "d" ] }, "how": { "fp32": "NVIDIA: “Single-Precision 16.3 TFLOPS” [nvidia.com]", "fp64": "Derived: FP32 ÷ 32 (this architecture's FP64 rate)", "fp16": "NVIDIA: “Tensor Performance 130.5 TFLOPS (no footnote on this row)” (precision not stated; Turing workstation and data-centre cards headline figures are FP16) [nvidia.com]", "int8": "Derived from NVIDIA's headline figure, 130.5 TFLOPS FP16. On Turing workstation and data-centre cards, INT8 runs at twice the FP16 rate", "int4": "Derived from NVIDIA's headline figure, 130.5 TFLOPS FP16. On Turing workstation and data-centre cards, INT4 runs at 4× the FP16 rate" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "tf32": "TF32 tensor cores arrived with Ampere", "bf16": "BF16 tensor cores arrived with Ampere", "fp8": "No FP8 tensor cores before Ada/Hopper (FP8 models run at FP16 speed)", "fp6": "No FP6 tensor cores before Blackwell", "fp4": "No FP4 tensor cores before Blackwell" }, "headline": "“Tensor Performance 130.5 TFLOPS (no footnote on this row)”", "anchor": "Derived from NVIDIA's headline figure, 130.5 TFLOPS FP16. ", "notes": "Archived NVIDIA product page lists 11 Giga Rays/Sec vs 10 for Quadro RTX 6000 despite the same config (not a precision figure).", "sources": [ { "t": "nvidia.com — /content/dam/en-zz/Solutions/design-visualization/quadro-product-literature/quad", "u": "https://www.nvidia.com/content/dam/en-zz/Solutions/design-visualization/quadro-product-literature/quadro-rtx-8000-us-nvidia-876688-r5-web.pdf" }, { "t": "web.archive.org — /web/20200525154801/https://www.nvidia.com/en-us/design-visualization/quadro/rtx", "u": "https://web.archive.org/web/20200525154801/https://www.nvidia.com/en-us/design-visualization/quadro/rtx-8000/" }, { "t": "techpowerup.com — /gpu-specs/quadro-rtx-8000.c3306", "u": "https://www.techpowerup.com/gpu-specs/quadro-rtx-8000.c3306" } ], "aka": null }, { "id": "quadro-gv100", "name": "NVIDIA Quadro GV100", "short": "Quadro GV100", "seg": "workstation", "arch": "Volta", "archGroup": "Volta", "cls": "volta", "clsLabel": "Volta (GV100)", "chip": "GV100", "date": "2018-03", "t": 2018.1666666666667, "status": null, "ff": "4.4\" H x 10.5\" L, dual slot, full height; active", "mem": 32.0, "memType": "HBM2", "bw": 870.0, "tdp": 250.0, "sms": null, "tc": 640.0, "cuda": 5120.0, "boost": 1627.0, "v": { "fp32": [ 14.8, null, "p" ], "fp64": [ 7.4, null, "p" ], "fp16": [ 118.5, null, "p" ] }, "how": { "fp32": "NVIDIA: “Single-Precision Performance 14.8 TFLOPS” [nvidia.com]", "fp64": "NVIDIA: “Double-Precision Performance 7.4 TFLOPS” [nvidia.com]", "fp16": "NVIDIA: “Tensor Performance 118.5 TFLOPS (no footnote on this row; datasheet footnotes 1-7 cover NVLink, adapters, Sync II, OS, Khronos, DX12)” (precision not stated; Volta headline figures are FP16) [nvidia.com]" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "tf32": "TF32 tensor cores arrived with Ampere", "bf16": "BF16 tensor cores arrived with Ampere", "fp8": "No FP8 tensor cores before Ada/Hopper (FP8 models run at FP16 speed)", "fp6": "No FP6 tensor cores before Blackwell", "fp4": "No FP4 tensor cores before Blackwell", "int8": "No INT8 tensor cores on this architecture", "int4": "No INT4 tensor cores on this architecture" }, "headline": "“Tensor Performance 118.5 TFLOPS (no footnote on this row; datasheet footnotes 1-7 cover NVLink, adapters, Sync II, OS, Khronos, DX12)”", "anchor": "Derived from NVIDIA's headline figure, 118.5 TFLOPS FP16. ", "notes": "Datasheet (Mar18) gives Tensor Performance with no precision/sparsity footnote.; TechPowerUp boost 1627 MHz looks inconsistent with NVIDIA's own rates (14.8 TFLOPS FP32 / 118.5 TFLOPS tensor imply a clock near 1.45 GHz); do not use 1627 MHz to derive throughput.; Volta architecture whitepaper covers Tesla V100 only; no NVIDIA table for Quadro GV100.; fp16_nontensor is from Leadtek (NVIDIA partner) because NVIDIA's product page no longer exists.", "sources": [ { "t": "nvidia.com — /content/dam/en-zz/Solutions/design-visualization/documents/quadro-pascal-gv100-", "u": "https://www.nvidia.com/content/dam/en-zz/Solutions/design-visualization/documents/quadro-pascal-gv100-us-nv-623049-r7-hr.pdf" }, { "t": "leadtek.com — /eng/products/workstation_graphics(2)/NVIDIA_Quadro_GV100(10798)/detail", "u": "https://www.leadtek.com/eng/products/workstation_graphics(2)/NVIDIA_Quadro_GV100(10798)/detail" }, { "t": "techpowerup.com — /gpu-specs/quadro-gv100.c3066", "u": "https://www.techpowerup.com/gpu-specs/quadro-gv100.c3066" } ], "aka": null }, { "id": "rtx-5090-d-v2", "name": "GeForce RTX 5090 D v2", "short": "RTX 5090 D v2", "seg": "geforce", "arch": "Blackwell", "archGroup": "Blackwell", "cls": "blackwell-geforce", "clsLabel": "Blackwell GB20x (GF)", "chip": "GB202", "date": "2025-08", "t": 2025.5833333333333, "status": null, "ff": null, "mem": 24.0, "memType": "GDDR7", "bw": 1344.0, "tdp": 575.0, "sms": 170.0, "tc": 680.0, "cuda": 21760.0, "boost": 2410.0, "v": { "fp32": [ 104.8832, null, "d" ], "fp64": [ 1.6388, null, "d" ], "fp4": [ 1187.5, 2375.0, "p" ] }, "how": { "fp32": "Derived: 2 × 21,760 CUDA cores × 2,410 MHz boost clock", "fp64": "Derived: FP32 ÷ 64 (this architecture's FP64 rate)", "fp4": "NVIDIA: “Tensor Core (AI) | 第 5 代 | 2375 AI TOPS” (dense = half the sparse figure) [nvidia.cn]" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "tf32": "NVIDIA cut this China-market card's AI throughput (2,375 vs 3,352 AI TOPS) without saying which tensor paths are slower, so only its published FP4 figure is shown", "fp16": "NVIDIA cut this China-market card's AI throughput (2,375 vs 3,352 AI TOPS) without saying which tensor paths are slower, so only its published FP4 figure is shown", "bf16": "NVIDIA cut this China-market card's AI throughput (2,375 vs 3,352 AI TOPS) without saying which tensor paths are slower, so only its published FP4 figure is shown", "fp8": "NVIDIA cut this China-market card's AI throughput (2,375 vs 3,352 AI TOPS) without saying which tensor paths are slower, so only its published FP4 figure is shown", "fp6": "RTX Blackwell supports FP6, but NVIDIA publishes no FP6 rate for it", "int8": "NVIDIA cut this China-market card's AI throughput (2,375 vs 3,352 AI TOPS) without saying which tensor paths are slower, so only its published FP4 figure is shown", "int4": "NVIDIA lists no INT4 rate for Blackwell" }, "headline": "“Tensor Core (AI) | 第 5 代 | 2375 AI TOPS” — read as FP4, sparse", "anchor": "Derived from NVIDIA's headline figure, 2,375 TFLOPS FP4 with sparsity (so 1,187.5 dense). ", "notes": "China-market 24 GB / 384-bit variant of the RTX 5090 D. No NVIDIA per-precision table; NVIDIA China page does not list shader TFLOPS. RT 318 TFLOPS on NVIDIA page.", "sources": [ { "t": "nvidia.cn — /geforce/graphics-cards/50-series/rtx-5090-d-v2/", "u": "https://www.nvidia.cn/geforce/graphics-cards/50-series/rtx-5090-d-v2/" }, { "t": "nvidia.cn — /geforce/graphics-cards/compare/", "u": "https://www.nvidia.cn/geforce/graphics-cards/compare/" }, { "t": "web.archive.org — /web/20250812185520/https://www.nvidia.cn/geforce/graphics-cards/50-series/rtx-5", "u": "https://web.archive.org/web/20250812185520/https://www.nvidia.cn/geforce/graphics-cards/50-series/rtx-5090-d-v2/" } ], "aka": null }, { "id": "rtx-5050", "name": "GeForce RTX 5050", "short": "RTX 5050", "seg": "geforce", "arch": "Blackwell", "archGroup": "Blackwell", "cls": "blackwell-geforce", "clsLabel": "Blackwell GB20x (GF)", "chip": "GB207", "date": "2025-07", "t": 2025.5, "status": null, "ff": null, "mem": 8.0, "memType": "GDDR6", "bw": 320.0, "tdp": 130.0, "sms": 20.0, "tc": 80.0, "cuda": 2560.0, "boost": 2570.0, "v": { "fp32": [ 13.1584, null, "d" ], "fp64": [ 0.2056, null, "d" ], "tf32": [ 13.1562, 26.3125, "d" ], "fp16": [ 26.3125, 52.625, "d" ], "bf16": [ 26.3125, 52.625, "d" ], "fp8": [ 52.625, 105.25, "d" ], "fp4": [ 210.5, 421.0, "p" ], "int8": [ 105.25, 210.5, "d" ], "fp8a16": [ 105.25, 210.5, "d" ], "fp16a16": [ 52.625, 105.25, "d" ] }, "how": { "fp32": "Derived: 2 × 2,560 CUDA cores × 2,570 MHz boost clock", "fp64": "Derived: FP32 ÷ 64 (this architecture's FP64 rate)", "tf32": "Derived from NVIDIA's headline figure, 421 TFLOPS FP4 with sparsity (so 210.5 dense). On GeForce Blackwell, TF32 runs at 0.0625× the FP4 rate", "fp16": "Derived from NVIDIA's headline figure, 421 TFLOPS FP4 with sparsity (so 210.5 dense). On GeForce Blackwell, FP16 (FP32 accumulate) runs at an eighth of the FP4 rate", "bf16": "Derived from NVIDIA's headline figure, 421 TFLOPS FP4 with sparsity (so 210.5 dense). On GeForce Blackwell, BF16 runs at an eighth of the FP4 rate", "fp8": "Derived from NVIDIA's headline figure, 421 TFLOPS FP4 with sparsity (so 210.5 dense). On GeForce Blackwell, FP8 (FP32 accumulate) runs at a quarter of the FP4 rate", "fp4": "NVIDIA: “Tensor Cores (AI) | 5th Generation | 421 AI TOPS” (dense = half the sparse figure) [nvidia.com]", "int8": "Derived from NVIDIA's headline figure, 421 TFLOPS FP4 with sparsity (so 210.5 dense). On GeForce Blackwell, INT8 runs at half the FP4 rate", "fp8a16": "Derived from NVIDIA's headline figure, 421 TFLOPS FP4 with sparsity (so 210.5 dense). On GeForce Blackwell, FP8 (FP16 accumulate) runs at half the FP4 rate", "fp16a16": "Derived from NVIDIA's headline figure, 421 TFLOPS FP4 with sparsity (so 210.5 dense). On GeForce Blackwell, FP16 (FP16 accumulate) runs at a quarter of the FP4 rate" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "fp6": "RTX Blackwell supports FP6, but NVIDIA publishes no FP6 rate for it", "int4": "NVIDIA lists no INT4 rate for Blackwell" }, "headline": "“Tensor Cores (AI) | 5th Generation | 421 AI TOPS” — read as FP4, sparse", "anchor": "Derived from NVIDIA's headline figure, 421 TFLOPS FP4 with sparsity (so 210.5 dense). ", "notes": "No NVIDIA per-precision table and no NVIDIA shader-TFLOPS figure found. RT 40 TFLOPS.", "sources": [ { "t": "nvidia.com — /en-us/geforce/graphics-cards/50-series/rtx-5050/", "u": "https://www.nvidia.com/en-us/geforce/graphics-cards/50-series/rtx-5050/" }, { "t": "nvidia.com — /en-us/geforce/graphics-cards/compare/", "u": "https://www.nvidia.com/en-us/geforce/graphics-cards/compare/" }, { "t": "nvidia.com — /en-us/geforce/news/rtx-5050-desktop-gpu-and-laptops/", "u": "https://www.nvidia.com/en-us/geforce/news/rtx-5050-desktop-gpu-and-laptops/" } ], "aka": null }, { "id": "rtx-5060", "name": "GeForce RTX 5060", "short": "RTX 5060", "seg": "geforce", "arch": "Blackwell", "archGroup": "Blackwell", "cls": "blackwell-geforce", "clsLabel": "Blackwell GB20x (GF)", "chip": "GB206", "date": "2025-05", "t": 2025.3333333333333, "status": null, "ff": null, "mem": 8.0, "memType": "GDDR7", "bw": 448.0, "tdp": 145.0, "sms": 30.0, "tc": 120.0, "cuda": 3840.0, "boost": 2500.0, "v": { "fp32": [ 19.0, null, "p" ], "fp64": [ 0.2969, null, "d" ], "tf32": [ 19.1875, 38.375, "d" ], "fp16": [ 38.375, 76.75, "d" ], "bf16": [ 38.375, 76.75, "d" ], "fp8": [ 76.75, 153.5, "d" ], "fp4": [ 307.0, 614.0, "p" ], "int8": [ 153.5, 307.0, "d" ], "fp8a16": [ 153.5, 307.0, "d" ], "fp16a16": [ 76.75, 153.5, "d" ] }, "how": { "fp32": "NVIDIA: “Shader Cores | Blackwell SM 19 TFLOPS” [nvidia.com]", "fp64": "Derived: FP32 ÷ 64 (this architecture's FP64 rate)", "tf32": "Derived from NVIDIA's headline figure, 614 TFLOPS FP4 with sparsity (so 307 dense). On GeForce Blackwell, TF32 runs at 0.0625× the FP4 rate", "fp16": "Derived from NVIDIA's headline figure, 614 TFLOPS FP4 with sparsity (so 307 dense). On GeForce Blackwell, FP16 (FP32 accumulate) runs at an eighth of the FP4 rate", "bf16": "Derived from NVIDIA's headline figure, 614 TFLOPS FP4 with sparsity (so 307 dense). On GeForce Blackwell, BF16 runs at an eighth of the FP4 rate", "fp8": "Derived from NVIDIA's headline figure, 614 TFLOPS FP4 with sparsity (so 307 dense). On GeForce Blackwell, FP8 (FP32 accumulate) runs at a quarter of the FP4 rate", "fp4": "NVIDIA: “Tensor Cores (AI) | 5th Generation | 614 AI TOPS” (dense = half the sparse figure) [nvidia.com]", "int8": "Derived from NVIDIA's headline figure, 614 TFLOPS FP4 with sparsity (so 307 dense). On GeForce Blackwell, INT8 runs at half the FP4 rate", "fp8a16": "Derived from NVIDIA's headline figure, 614 TFLOPS FP4 with sparsity (so 307 dense). On GeForce Blackwell, FP8 (FP16 accumulate) runs at half the FP4 rate", "fp16a16": "Derived from NVIDIA's headline figure, 614 TFLOPS FP4 with sparsity (so 307 dense). On GeForce Blackwell, FP16 (FP16 accumulate) runs at a quarter of the FP4 rate" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "fp6": "RTX Blackwell supports FP6, but NVIDIA publishes no FP6 rate for it", "int4": "NVIDIA lists no INT4 rate for Blackwell" }, "headline": "“Tensor Cores (AI) | 5th Generation | 614 AI TOPS” — read as FP4, sparse", "anchor": "Derived from NVIDIA's headline figure, 614 TFLOPS FP4 with sparsity (so 307 dense). ", "notes": "No NVIDIA per-precision table. RT 58 TFLOPS.", "sources": [ { "t": "nvidia.com — /en-us/geforce/graphics-cards/50-series/rtx-5060-family/", "u": "https://www.nvidia.com/en-us/geforce/graphics-cards/50-series/rtx-5060-family/" }, { "t": "nvidia.com — /en-us/geforce/graphics-cards/compare/", "u": "https://www.nvidia.com/en-us/geforce/graphics-cards/compare/" }, { "t": "nvidianews.nvidia.com — /news/nvidia-blackwell-geforce-rtx-arrives-for-every-gamer-starting-at-299", "u": "https://nvidianews.nvidia.com/news/nvidia-blackwell-geforce-rtx-arrives-for-every-gamer-starting-at-299" }, { "t": "nvidia.com — /en-us/geforce/news/rtx-5060-out-now/", "u": "https://www.nvidia.com/en-us/geforce/news/rtx-5060-out-now/" }, { "t": "nvidia.com — /content/dam/en-zz/Solutions/geforce/news/rtx-5060-desktop-family-laptop-5060-co", "u": "https://www.nvidia.com/content/dam/en-zz/Solutions/geforce/news/rtx-5060-desktop-family-laptop-5060-coming-soon/geforce-rtx-5060-desktop-family-specification-comparison.png" } ], "aka": null }, { "id": "rtx-5060-ti-16gb", "name": "GeForce RTX 5060 Ti 16GB", "short": "RTX 5060 Ti 16GB", "seg": "geforce", "arch": "Blackwell", "archGroup": "Blackwell", "cls": "blackwell-geforce", "clsLabel": "Blackwell GB20x (GF)", "chip": "GB206", "date": "2025-04", "t": 2025.25, "status": null, "ff": null, "mem": 16.0, "memType": "GDDR7", "bw": 448.0, "tdp": 180.0, "sms": 36.0, "tc": 144.0, "cuda": 4608.0, "boost": 2570.0, "v": { "fp32": [ 24.0, null, "p" ], "fp64": [ 0.375, null, "d" ], "tf32": [ 23.7188, 47.4375, "d" ], "fp16": [ 47.4375, 94.875, "d" ], "bf16": [ 47.4375, 94.875, "d" ], "fp8": [ 94.875, 189.75, "d" ], "fp4": [ 379.5, 759.0, "p" ], "int8": [ 189.75, 379.5, "d" ], "fp8a16": [ 189.75, 379.5, "d" ], "fp16a16": [ 94.875, 189.75, "d" ] }, "how": { "fp32": "NVIDIA: “Shader Cores | Blackwell SM 24 TFLOPS” [nvidia.com]", "fp64": "Derived: FP32 ÷ 64 (this architecture's FP64 rate)", "tf32": "Derived from NVIDIA's headline figure, 759 TFLOPS FP4 with sparsity (so 379.5 dense). On GeForce Blackwell, TF32 runs at 0.0625× the FP4 rate", "fp16": "Derived from NVIDIA's headline figure, 759 TFLOPS FP4 with sparsity (so 379.5 dense). On GeForce Blackwell, FP16 (FP32 accumulate) runs at an eighth of the FP4 rate", "bf16": "Derived from NVIDIA's headline figure, 759 TFLOPS FP4 with sparsity (so 379.5 dense). On GeForce Blackwell, BF16 runs at an eighth of the FP4 rate", "fp8": "Derived from NVIDIA's headline figure, 759 TFLOPS FP4 with sparsity (so 379.5 dense). On GeForce Blackwell, FP8 (FP32 accumulate) runs at a quarter of the FP4 rate", "fp4": "NVIDIA: “Tensor Cores (AI) | 5th Generation | 759 AI TOPS” (dense = half the sparse figure) [nvidia.com]", "int8": "Derived from NVIDIA's headline figure, 759 TFLOPS FP4 with sparsity (so 379.5 dense). On GeForce Blackwell, INT8 runs at half the FP4 rate", "fp8a16": "Derived from NVIDIA's headline figure, 759 TFLOPS FP4 with sparsity (so 379.5 dense). On GeForce Blackwell, FP8 (FP16 accumulate) runs at half the FP4 rate", "fp16a16": "Derived from NVIDIA's headline figure, 759 TFLOPS FP4 with sparsity (so 379.5 dense). On GeForce Blackwell, FP16 (FP16 accumulate) runs at a quarter of the FP4 rate" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "fp6": "RTX Blackwell supports FP6, but NVIDIA publishes no FP6 rate for it", "int4": "NVIDIA lists no INT4 rate for Blackwell" }, "headline": "“Tensor Cores (AI) | 5th Generation | 759 AI TOPS” — read as FP4, sparse", "anchor": "Derived from NVIDIA's headline figure, 759 TFLOPS FP4 with sparsity (so 379.5 dense). ", "notes": "8 GB and 16 GB versions share all published compute specs. No NVIDIA per-precision table (RTX Blackwell whitepaper V1.1 covers only GB202/GB203/GB205). RT 72 TFLOPS.", "sources": [ { "t": "nvidia.com — /en-us/geforce/graphics-cards/50-series/rtx-5060-family/", "u": "https://www.nvidia.com/en-us/geforce/graphics-cards/50-series/rtx-5060-family/" }, { "t": "nvidia.com — /en-us/geforce/graphics-cards/compare/", "u": "https://www.nvidia.com/en-us/geforce/graphics-cards/compare/" }, { "t": "nvidianews.nvidia.com — /news/nvidia-blackwell-geforce-rtx-arrives-for-every-gamer-starting-at-299", "u": "https://nvidianews.nvidia.com/news/nvidia-blackwell-geforce-rtx-arrives-for-every-gamer-starting-at-299" }, { "t": "nvidia.com — /en-us/geforce/news/rtx-5060-desktop-family-laptop-5060-coming-soon/", "u": "https://www.nvidia.com/en-us/geforce/news/rtx-5060-desktop-family-laptop-5060-coming-soon/" }, { "t": "nvidia.com — /content/dam/en-zz/Solutions/geforce/news/rtx-5060-desktop-family-laptop-5060-co", "u": "https://www.nvidia.com/content/dam/en-zz/Solutions/geforce/news/rtx-5060-desktop-family-laptop-5060-coming-soon/geforce-rtx-5060-desktop-family-specification-comparison.png" } ], "aka": null }, { "id": "rtx-5060-ti-8gb", "name": "GeForce RTX 5060 Ti 8GB", "short": "RTX 5060 Ti 8GB", "seg": "geforce", "arch": "Blackwell", "archGroup": "Blackwell", "cls": "blackwell-geforce", "clsLabel": "Blackwell GB20x (GF)", "chip": "GB206", "date": "2025-04", "t": 2025.25, "status": null, "ff": null, "mem": 8.0, "memType": "GDDR7", "bw": 448.0, "tdp": 180.0, "sms": 36.0, "tc": 144.0, "cuda": 4608.0, "boost": 2570.0, "v": { "fp32": [ 24.0, null, "p" ], "fp64": [ 0.375, null, "d" ], "tf32": [ 23.7188, 47.4375, "d" ], "fp16": [ 47.4375, 94.875, "d" ], "bf16": [ 47.4375, 94.875, "d" ], "fp8": [ 94.875, 189.75, "d" ], "fp4": [ 379.5, 759.0, "p" ], "int8": [ 189.75, 379.5, "d" ], "fp8a16": [ 189.75, 379.5, "d" ], "fp16a16": [ 94.875, 189.75, "d" ] }, "how": { "fp32": "NVIDIA: “Shader Cores | Blackwell SM 24 TFLOPS” [nvidia.com]", "fp64": "Derived: FP32 ÷ 64 (this architecture's FP64 rate)", "tf32": "Derived from NVIDIA's headline figure, 759 TFLOPS FP4 with sparsity (so 379.5 dense). On GeForce Blackwell, TF32 runs at 0.0625× the FP4 rate", "fp16": "Derived from NVIDIA's headline figure, 759 TFLOPS FP4 with sparsity (so 379.5 dense). On GeForce Blackwell, FP16 (FP32 accumulate) runs at an eighth of the FP4 rate", "bf16": "Derived from NVIDIA's headline figure, 759 TFLOPS FP4 with sparsity (so 379.5 dense). On GeForce Blackwell, BF16 runs at an eighth of the FP4 rate", "fp8": "Derived from NVIDIA's headline figure, 759 TFLOPS FP4 with sparsity (so 379.5 dense). On GeForce Blackwell, FP8 (FP32 accumulate) runs at a quarter of the FP4 rate", "fp4": "NVIDIA: “Tensor Cores (AI) | 5th Generation | 759 AI TOPS” (dense = half the sparse figure) [nvidia.com]", "int8": "Derived from NVIDIA's headline figure, 759 TFLOPS FP4 with sparsity (so 379.5 dense). On GeForce Blackwell, INT8 runs at half the FP4 rate", "fp8a16": "Derived from NVIDIA's headline figure, 759 TFLOPS FP4 with sparsity (so 379.5 dense). On GeForce Blackwell, FP8 (FP16 accumulate) runs at half the FP4 rate", "fp16a16": "Derived from NVIDIA's headline figure, 759 TFLOPS FP4 with sparsity (so 379.5 dense). On GeForce Blackwell, FP16 (FP16 accumulate) runs at a quarter of the FP4 rate" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "fp6": "RTX Blackwell supports FP6, but NVIDIA publishes no FP6 rate for it", "int4": "NVIDIA lists no INT4 rate for Blackwell" }, "headline": "“Tensor Cores (AI) | 5th Generation | 759 AI TOPS” — read as FP4, sparse", "anchor": "Derived from NVIDIA's headline figure, 759 TFLOPS FP4 with sparsity (so 379.5 dense). ", "notes": "8 GB and 16 GB versions share all published compute specs. No NVIDIA per-precision table (RTX Blackwell whitepaper V1.1 covers only GB202/GB203/GB205). RT 72 TFLOPS.", "sources": [ { "t": "nvidia.com — /en-us/geforce/graphics-cards/50-series/rtx-5060-family/", "u": "https://www.nvidia.com/en-us/geforce/graphics-cards/50-series/rtx-5060-family/" }, { "t": "nvidia.com — /en-us/geforce/graphics-cards/compare/", "u": "https://www.nvidia.com/en-us/geforce/graphics-cards/compare/" }, { "t": "nvidianews.nvidia.com — /news/nvidia-blackwell-geforce-rtx-arrives-for-every-gamer-starting-at-299", "u": "https://nvidianews.nvidia.com/news/nvidia-blackwell-geforce-rtx-arrives-for-every-gamer-starting-at-299" }, { "t": "nvidia.com — /en-us/geforce/news/rtx-5060-desktop-family-laptop-5060-coming-soon/", "u": "https://www.nvidia.com/en-us/geforce/news/rtx-5060-desktop-family-laptop-5060-coming-soon/" }, { "t": "nvidia.com — /content/dam/en-zz/Solutions/geforce/news/rtx-5060-desktop-family-laptop-5060-co", "u": "https://www.nvidia.com/content/dam/en-zz/Solutions/geforce/news/rtx-5060-desktop-family-laptop-5060-coming-soon/geforce-rtx-5060-desktop-family-specification-comparison.png" } ], "aka": null }, { "id": "rtx-5070", "name": "GeForce RTX 5070", "short": "RTX 5070", "seg": "geforce", "arch": "Blackwell", "archGroup": "Blackwell", "cls": "blackwell-geforce", "clsLabel": "Blackwell GB20x (GF)", "chip": "GB205", "date": "2025-03", "t": 2025.1666666666667, "status": null, "ff": null, "mem": 12.0, "memType": "GDDR7", "bw": 672.0, "tdp": 250.0, "sms": 48.0, "tc": 192.0, "cuda": 6144.0, "boost": 2512.0, "v": { "fp32": [ 30.9, null, "p" ], "fp64": [ 0.4828, null, "d" ], "tf32": [ 30.9, 61.7, "p" ], "fp16": [ 61.7, 123.5, "p" ], "bf16": [ 61.7, 123.5, "p" ], "fp8": [ 123.5, 246.9, "p" ], "fp4": [ 493.9, 987.8, "p" ], "int8": [ 246.9, 493.9, "p" ], "fp8a16": [ 246.9, 493.9, "p" ], "fp16a16": [ 123.5, 246.9, "p" ] }, "how": { "fp32": "NVIDIA: “Peak FP32 TFLOPS (non-Tensor)^1 | 30.9” [images.nvidia.com]", "fp64": "Derived: FP32 ÷ 64 (this architecture's FP64 rate)", "tf32": "NVIDIA: “Peak TF32 Tensor TFLOPS^1 | 30.9/61.7^2” [images.nvidia.com]", "fp16": "NVIDIA: “Peak FP16 Tensor TFLOPS with FP32 Accumulate^1 | 61.7/123.5^2” [images.nvidia.com]", "bf16": "NVIDIA: “Peak BF16 Tensor TFLOPS with FP32 Accumulate^1 | 61.7/123.5^2” [images.nvidia.com]", "fp8": "NVIDIA: “Peak FP8 Tensor TFLOPS with FP32 Accumulate^1 | 123.5/246.9^2” [images.nvidia.com]", "fp4": "NVIDIA: “Peak FP4 Tensor TFLOPS with FP32 Accumulate (FP4 AI TOPS) | 493.9/987.8^2” [images.nvidia.com] (accumulate type inferred)", "int8": "NVIDIA: “Peak INT8 Tensor TOPS^1 | 246.9/493.9^2” [images.nvidia.com]", "fp8a16": "NVIDIA: “Peak FP8 Tensor TFLOPS with FP16 Accumulate^1 | 246.9/493.9^2” [images.nvidia.com]", "fp16a16": "NVIDIA: “Peak FP16 Tensor TFLOPS with FP16 Accumulate^1 | 123.5/246.9^2” [images.nvidia.com]" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "fp6": "RTX Blackwell supports FP6, but NVIDIA publishes no FP6 rate for it", "int4": "NVIDIA lists no INT4 rate for Blackwell" }, "headline": "“Tensor Cores (AI) | 5th Generation | 988 AI TOPS” — read as FP4, sparse", "anchor": "Derived from NVIDIA's published FP16 (FP16 accumulate) figure of 123.5 dense. ", "notes": "RTX Blackwell whitepaper V1.1 Appendix C Table 6 (the appendix text calls it 'The Ada GB205 GPU', a typo). No FP6 or INT4 rows. Product page RT 94 TFLOPS.", "sources": [ { "t": "images.nvidia.com — /aem-dam/Solutions/geforce/blackwell/nvidia-rtx-blackwell-gpu-architecture.pdf", "u": "https://images.nvidia.com/aem-dam/Solutions/geforce/blackwell/nvidia-rtx-blackwell-gpu-architecture.pdf" }, { "t": "nvidia.com — /en-us/geforce/graphics-cards/50-series/rtx-5070-family/", "u": "https://www.nvidia.com/en-us/geforce/graphics-cards/50-series/rtx-5070-family/" }, { "t": "nvidia.com — /en-us/geforce/graphics-cards/compare/", "u": "https://www.nvidia.com/en-us/geforce/graphics-cards/compare/" }, { "t": "nvidia.com — /en-us/geforce/news/rtx-5070-out-now/", "u": "https://www.nvidia.com/en-us/geforce/news/rtx-5070-out-now/" }, { "t": "nvidianews.nvidia.com — /news/nvidia-blackwell-geforce-rtx-50-series-opens-new-world-of-ai-computer-grap", "u": "https://nvidianews.nvidia.com/news/nvidia-blackwell-geforce-rtx-50-series-opens-new-world-of-ai-computer-graphics" } ], "aka": null }, { "id": "rtx-5070-ti", "name": "GeForce RTX 5070 Ti", "short": "RTX 5070 Ti", "seg": "geforce", "arch": "Blackwell", "archGroup": "Blackwell", "cls": "blackwell-geforce", "clsLabel": "Blackwell GB20x (GF)", "chip": "GB203", "date": "2025-02", "t": 2025.0833333333333, "status": null, "ff": null, "mem": 16.0, "memType": "GDDR7", "bw": 896.0, "tdp": 300.0, "sms": 70.0, "tc": 280.0, "cuda": 8960.0, "boost": 2452.0, "v": { "fp32": [ 43.9, null, "p" ], "fp64": [ 0.6859, null, "d" ], "tf32": [ 43.9, 87.9, "p" ], "fp16": [ 87.9, 175.8, "p" ], "bf16": [ 87.9, 175.8, "p" ], "fp8": [ 175.8, 351.5, "p" ], "fp4": [ 703.0, 1406.0, "p" ], "int8": [ 351.5, 703.0, "p" ], "fp8a16": [ 351.5, 703.0, "p" ], "fp16a16": [ 175.8, 351.5, "p" ] }, "how": { "fp32": "NVIDIA: “Peak FP32 TFLOPS (non-Tensor)^1 | 43.9” [images.nvidia.com]", "fp64": "Derived: FP32 ÷ 64 (this architecture's FP64 rate)", "tf32": "NVIDIA: “Peak TF32 Tensor TFLOPS^1 | 43.9/87.9^2” [images.nvidia.com]", "fp16": "NVIDIA: “Peak FP16 Tensor TFLOPS with FP32 Accumulate^1 | 87.9/175.8^2” [images.nvidia.com]", "bf16": "NVIDIA: “Peak BF16 Tensor TFLOPS with FP32 Accumulate^1 | 87.9/175.8^2” [images.nvidia.com]", "fp8": "NVIDIA: “Peak FP8 Tensor TFLOPS with FP32 Accumulate^1 | 175.8/351.5^2” [images.nvidia.com]", "fp4": "NVIDIA: “Peak FP4 Tensor TFLOPS with FP32 Accumulate (FP4 AI TOPS) | 703/1406^2” [images.nvidia.com] (accumulate type inferred)", "int8": "NVIDIA: “Peak INT8 Tensor TOPS^1 | 351.5/703^2” [images.nvidia.com]", "fp8a16": "NVIDIA: “Peak FP8 Tensor TFLOPS with FP16 Accumulate^1 | 351.5/703^2” [images.nvidia.com]", "fp16a16": "NVIDIA: “Peak FP16 Tensor TFLOPS with FP16 Accumulate^1 | 175.8/351.5^2” [images.nvidia.com]" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "fp6": "RTX Blackwell supports FP6, but NVIDIA publishes no FP6 rate for it", "int4": "NVIDIA lists no INT4 rate for Blackwell" }, "headline": "“Tensor Cores (AI) | 5th Generation | 1406 AI TOPS” — read as FP4, sparse", "anchor": "Derived from NVIDIA's published FP16 (FP16 accumulate) figure of 175.8 dense. ", "notes": "RTX Blackwell whitepaper V1.1 Appendix B Table 5. No FP6 or INT4 rows. Product page RT 133 TFLOPS.", "sources": [ { "t": "images.nvidia.com — /aem-dam/Solutions/geforce/blackwell/nvidia-rtx-blackwell-gpu-architecture.pdf", "u": "https://images.nvidia.com/aem-dam/Solutions/geforce/blackwell/nvidia-rtx-blackwell-gpu-architecture.pdf" }, { "t": "nvidia.com — /en-us/geforce/graphics-cards/50-series/rtx-5070-family/", "u": "https://www.nvidia.com/en-us/geforce/graphics-cards/50-series/rtx-5070-family/" }, { "t": "nvidia.com — /en-us/geforce/graphics-cards/compare/", "u": "https://www.nvidia.com/en-us/geforce/graphics-cards/compare/" }, { "t": "nvidia.com — /en-us/geforce/news/rtx-5070-ti-out-now/", "u": "https://www.nvidia.com/en-us/geforce/news/rtx-5070-ti-out-now/" }, { "t": "nvidianews.nvidia.com — /news/nvidia-blackwell-geforce-rtx-50-series-opens-new-world-of-ai-computer-grap", "u": "https://nvidianews.nvidia.com/news/nvidia-blackwell-geforce-rtx-50-series-opens-new-world-of-ai-computer-graphics" } ], "aka": null }, { "id": "rtx-5080", "name": "GeForce RTX 5080", "short": "RTX 5080", "seg": "geforce", "arch": "Blackwell", "archGroup": "Blackwell", "cls": "blackwell-geforce", "clsLabel": "Blackwell GB20x (GF)", "chip": "GB203", "date": "2025-01", "t": 2025.0, "status": null, "ff": null, "mem": 16.0, "memType": "GDDR7", "bw": 960.0, "tdp": 360.0, "sms": 84.0, "tc": 336.0, "cuda": 10752.0, "boost": 2617.0, "v": { "fp32": [ 56.3, null, "p" ], "fp64": [ 0.8797, null, "d" ], "tf32": [ 56.3, 112.6, "p" ], "fp16": [ 112.6, 225.1, "p" ], "bf16": [ 112.6, 225.1, "p" ], "fp8": [ 225.1, 450.2, "p" ], "fp4": [ 900.4, 1801.0, "p" ], "int8": [ 450.2, 900.4, "p" ], "fp8a16": [ 450.2, 900.4, "p" ], "fp16a16": [ 225.1, 450.2, "p" ] }, "how": { "fp32": "NVIDIA: “Peak FP32 TFLOPS (non-Tensor)^1 | 56.3” [images.nvidia.com]", "fp64": "Derived: FP32 ÷ 64 (this architecture's FP64 rate)", "tf32": "NVIDIA: “Peak TF32 Tensor TFLOPS^1 | 56.3/112.6^2” [images.nvidia.com]", "fp16": "NVIDIA: “Peak FP16 Tensor TFLOPS with FP32 Accumulate^1 | 112.6/225.1^2” [images.nvidia.com]", "bf16": "NVIDIA: “Peak BF16 Tensor TFLOPS with FP32 Accumulate^1 | 112.6/225.1^2” [images.nvidia.com]", "fp8": "NVIDIA: “Peak FP8 Tensor TFLOPS with FP32 Accumulate^1 | 225.1/450.2^2” [images.nvidia.com]", "fp4": "NVIDIA: “Peak FP4 Tensor TFLOPS with FP32 Accumulate (FP4 AI TOPS) | 900.4/1801^2” [images.nvidia.com] (accumulate type inferred)", "int8": "NVIDIA: “Peak INT8 Tensor TOPS^1 | 450.2/900.4^2” [images.nvidia.com]", "fp8a16": "NVIDIA: “Peak FP8 Tensor TFLOPS with FP16 Accumulate^1 | 450.2/900.4^2” [images.nvidia.com]", "fp16a16": "NVIDIA: “Peak FP16 Tensor TFLOPS with FP16 Accumulate^1 | 225.1/450.2^2” [images.nvidia.com]" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "fp6": "RTX Blackwell supports FP6, but NVIDIA publishes no FP6 rate for it", "int4": "NVIDIA lists no INT4 rate for Blackwell" }, "headline": "“Tensor Cores (AI) | 5th Generation | 1801 AI TOPS” — read as FP4, sparse", "anchor": "Derived from NVIDIA's published FP16 (FP16 accumulate) figure of 225.1 dense. ", "notes": "RTX Blackwell whitepaper V1.1 Appendix B Table 4. No FP6 or INT4 rows. Product page RT 171 TFLOPS (whitepaper 170.6).", "sources": [ { "t": "images.nvidia.com — /aem-dam/Solutions/geforce/blackwell/nvidia-rtx-blackwell-gpu-architecture.pdf", "u": "https://images.nvidia.com/aem-dam/Solutions/geforce/blackwell/nvidia-rtx-blackwell-gpu-architecture.pdf" }, { "t": "nvidia.com — /en-us/geforce/graphics-cards/50-series/rtx-5080/", "u": "https://www.nvidia.com/en-us/geforce/graphics-cards/50-series/rtx-5080/" }, { "t": "nvidia.com — /en-us/geforce/graphics-cards/compare/", "u": "https://www.nvidia.com/en-us/geforce/graphics-cards/compare/" }, { "t": "nvidianews.nvidia.com — /news/nvidia-blackwell-geforce-rtx-50-series-opens-new-world-of-ai-computer-grap", "u": "https://nvidianews.nvidia.com/news/nvidia-blackwell-geforce-rtx-50-series-opens-new-world-of-ai-computer-graphics" } ], "aka": null }, { "id": "rtx-5090", "name": "GeForce RTX 5090", "short": "RTX 5090", "seg": "geforce", "arch": "Blackwell", "archGroup": "Blackwell", "cls": "blackwell-geforce", "clsLabel": "Blackwell GB20x (GF)", "chip": "GB202", "date": "2025-01", "t": 2025.0, "status": null, "ff": null, "mem": 32.0, "memType": "GDDR7", "bw": 1792.0, "tdp": 575.0, "sms": 170.0, "tc": 680.0, "cuda": 21760.0, "boost": 2407.0, "v": { "fp32": [ 104.8, null, "p" ], "fp64": [ 1.6375, null, "d" ], "tf32": [ 104.8, 209.5, "p" ], "fp16": [ 209.5, 419.0, "p" ], "bf16": [ 209.5, 419.0, "p" ], "fp8": [ 419.0, 838.0, "p" ], "fp4": [ 1676.0, 3352.0, "p" ], "int8": [ 838.0, 1676.0, "p" ], "fp8a16": [ 838.0, 1676.0, "p" ], "fp16a16": [ 419.0, 838.0, "p" ] }, "how": { "fp32": "NVIDIA: “Peak FP32 TFLOPS (non-Tensor)^1 | 104.8” [images.nvidia.com]", "fp64": "Derived: FP32 ÷ 64 (this architecture's FP64 rate)", "tf32": "NVIDIA: “Peak TF32 Tensor TFLOPS^1 | 104.8/209.5^2” [images.nvidia.com]", "fp16": "NVIDIA: “Peak FP16 Tensor TFLOPS with FP32 Accumulate^1 | 209.5/419^2” [images.nvidia.com]", "bf16": "NVIDIA: “Peak BF16 Tensor TFLOPS with FP32 Accumulate^1 | 209.5/419^2” [images.nvidia.com]", "fp8": "NVIDIA: “Peak FP8 Tensor TFLOPS with FP32 Accumulate^1 | 419/838^2” [images.nvidia.com]", "fp4": "NVIDIA: “Peak FP4 Tensor TFLOPS with FP32 Accumulate (FP4 AI TOPS) | 1676/3352^2” [images.nvidia.com] (accumulate type inferred)", "int8": "NVIDIA: “Peak INT8 Tensor TOPS^1 | 838/1676^2” [images.nvidia.com]", "fp8a16": "NVIDIA: “Peak FP8 Tensor TFLOPS with FP16 Accumulate^1 | 838/1676^2” [images.nvidia.com]", "fp16a16": "NVIDIA: “Peak FP16 Tensor TFLOPS with FP16 Accumulate^1 | 419/838^2” [images.nvidia.com]" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "fp6": "RTX Blackwell supports FP6, but NVIDIA publishes no FP6 rate for it", "int4": "NVIDIA lists no INT4 rate for Blackwell" }, "headline": "“Tensor Cores (AI) | 5th Generation | 3352 AI TOPS” — read as FP4, sparse", "anchor": "Derived from NVIDIA's published FP16 (FP16 accumulate) figure of 419 dense. ", "notes": "RTX Blackwell whitepaper V1.1 Appendix A Table 3. Half-rate pattern as printed: FP16/FP8 with FP32 accumulate, BF16 and TF32 are half the FP16-accumulate rates; FP4 is printed only 'with FP32 Accumulate' at 2x the FP8 FP16-accumulate rate. No FP6 or INT4 rows. Whitepaper: GB202 has 384 FP64 cores, 'The FP64 TFLOP rate is 1/64th the TFLOP rate of FP32 operations' (no absolute number). Product page: RT 318 TFLOPS (whitepaper 317.5).", "sources": [ { "t": "images.nvidia.com — /aem-dam/Solutions/geforce/blackwell/nvidia-rtx-blackwell-gpu-architecture.pdf", "u": "https://images.nvidia.com/aem-dam/Solutions/geforce/blackwell/nvidia-rtx-blackwell-gpu-architecture.pdf" }, { "t": "nvidia.com — /en-us/geforce/graphics-cards/50-series/rtx-5090/", "u": "https://www.nvidia.com/en-us/geforce/graphics-cards/50-series/rtx-5090/" }, { "t": "nvidia.com — /en-us/geforce/graphics-cards/compare/", "u": "https://www.nvidia.com/en-us/geforce/graphics-cards/compare/" }, { "t": "nvidianews.nvidia.com — /news/nvidia-blackwell-geforce-rtx-50-series-opens-new-world-of-ai-computer-grap", "u": "https://nvidianews.nvidia.com/news/nvidia-blackwell-geforce-rtx-50-series-opens-new-world-of-ai-computer-graphics" } ], "aka": null }, { "id": "rtx-5090-d", "name": "GeForce RTX 5090 D", "short": "RTX 5090 D", "seg": "geforce", "arch": "Blackwell", "archGroup": "Blackwell", "cls": "blackwell-geforce", "clsLabel": "Blackwell GB20x (GF)", "chip": "GB202", "date": "2025-01", "t": 2025.0, "status": null, "ff": null, "mem": 32.0, "memType": "GDDR7", "bw": null, "tdp": 575.0, "sms": 170.0, "tc": 680.0, "cuda": 21760.0, "boost": 2410.0, "v": { "fp32": [ 104.8832, null, "d" ], "fp64": [ 1.6388, null, "d" ], "fp4": [ 1187.5, 2375.0, "p" ] }, "how": { "fp32": "Derived: 2 × 21,760 CUDA cores × 2,410 MHz boost clock", "fp64": "Derived: FP32 ÷ 64 (this architecture's FP64 rate)", "fp4": "NVIDIA: “Tensor Core (AI) | 第 5 代 | 2375 AI TOPS” (dense = half the sparse figure) [web.archive.org]" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "tf32": "NVIDIA cut this China-market card's AI throughput (2,375 vs 3,352 AI TOPS) without saying which tensor paths are slower, so only its published FP4 figure is shown", "fp16": "NVIDIA cut this China-market card's AI throughput (2,375 vs 3,352 AI TOPS) without saying which tensor paths are slower, so only its published FP4 figure is shown", "bf16": "NVIDIA cut this China-market card's AI throughput (2,375 vs 3,352 AI TOPS) without saying which tensor paths are slower, so only its published FP4 figure is shown", "fp8": "NVIDIA cut this China-market card's AI throughput (2,375 vs 3,352 AI TOPS) without saying which tensor paths are slower, so only its published FP4 figure is shown", "fp6": "RTX Blackwell supports FP6, but NVIDIA publishes no FP6 rate for it", "int8": "NVIDIA cut this China-market card's AI throughput (2,375 vs 3,352 AI TOPS) without saying which tensor paths are slower, so only its published FP4 figure is shown", "int4": "NVIDIA lists no INT4 rate for Blackwell" }, "headline": "“Tensor Core (AI) | 第 5 代 | 2375 AI TOPS” — read as FP4, sparse", "anchor": "Derived from NVIDIA's headline figure, 2,375 TFLOPS FP4 with sparsity (so 1,187.5 dense). ", "notes": "Original China-market RTX 5090 D (32 GB). NVIDIA's China page now redirects to the 5090 D v2. No NVIDIA per-precision table; NVIDIA China page does not list shader TFLOPS. RT 318 TFLOPS on NVIDIA page.", "sources": [ { "t": "web.archive.org — /web/20250310021605/https://www.nvidia.cn/geforce/graphics-cards/50-series/rtx-5", "u": "https://web.archive.org/web/20250310021605/https://www.nvidia.cn/geforce/graphics-cards/50-series/rtx-5090-d/" }, { "t": "web.archive.org — /web/20250617205105/https://www.nvidia.cn/geforce/graphics-cards/compare/", "u": "https://web.archive.org/web/20250617205105/https://www.nvidia.cn/geforce/graphics-cards/compare/" }, { "t": "nvidia.cn — /geforce/graphics-cards/compare/", "u": "https://www.nvidia.cn/geforce/graphics-cards/compare/" } ], "aka": null }, { "id": "rtx-3050-6gb", "name": "GeForce RTX 3050 6GB", "short": "RTX 3050 6GB", "seg": "geforce", "arch": "Ampere", "archGroup": "Ampere", "cls": "ampere-geforce", "clsLabel": "Ampere GA10x (GF)", "chip": "GA107", "date": "2024-02", "t": 2024.0833333333333, "status": null, "ff": "desktop PCIe card", "mem": 6.0, "memType": "GDDR6", "bw": 168.0, "tdp": 70.0, "sms": 18.0, "tc": 72.0, "cuda": 2304.0, "boost": 1470.0, "v": { "fp32": [ 6.7738, null, "d" ], "fp64": [ 0.1058, null, "d" ], "tf32": [ 6.7738, 13.5475, "d" ], "fp16": [ 13.5475, 27.095, "d" ], "bf16": [ 13.5475, 27.095, "d" ], "int8": [ 54.1901, 108.3802, "d" ], "int4": [ 108.3802, 216.7603, "d" ], "fp16a16": [ 27.095, 54.1901, "d" ] }, "how": { "fp32": "Derived: 2 × 2,304 CUDA cores × 1,470 MHz boost clock", "fp64": "Derived: FP32 ÷ 64 (this architecture's FP64 rate)", "tf32": "Derived: 18 SMs × 1,470 MHz boost clock × 256 TF32 ops per clock per SM on GeForce Ampere. NVIDIA publishes no tensor figure for this card", "fp16": "Derived: 18 SMs × 1,470 MHz boost clock × 512 FP16 (FP32 accumulate) ops per clock per SM on GeForce Ampere. NVIDIA publishes no tensor figure for this card", "bf16": "Derived: 18 SMs × 1,470 MHz boost clock × 512 BF16 ops per clock per SM on GeForce Ampere. NVIDIA publishes no tensor figure for this card", "int8": "Derived: 18 SMs × 1,470 MHz boost clock × 2,048 INT8 ops per clock per SM on GeForce Ampere. NVIDIA publishes no tensor figure for this card", "int4": "Derived: 18 SMs × 1,470 MHz boost clock × 4,096 INT4 ops per clock per SM on GeForce Ampere. NVIDIA publishes no tensor figure for this card", "fp16a16": "Derived: 18 SMs × 1,470 MHz boost clock × 1,024 FP16 (FP16 accumulate) ops per clock per SM on GeForce Ampere. NVIDIA publishes no tensor figure for this card" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "fp8": "No FP8 tensor cores before Ada/Hopper (FP8 models run at FP16 speed)", "fp6": "No FP6 tensor cores before Blackwell", "fp4": "No FP4 tensor cores before Blackwell" }, "headline": null, "anchor": "Derived from 18 SMs × 1,470 MHz boost clock. ", "notes": "NVIDIA published no throughput figure and made no announcement. The card only appears as a column on the RTX 3050 spec page and the compare page. Bus-powered (no supplementary connector, per NVIDIA page). No Founders Edition.", "sources": [ { "t": "nvidia.com — /en-us/geforce/graphics-cards/30-series/rtx-3050/", "u": "https://www.nvidia.com/en-us/geforce/graphics-cards/30-series/rtx-3050/" }, { "t": "pny.com — /geforce-rtx-3050-6gb-verto-dual-fan", "u": "https://www.pny.com/geforce-rtx-3050-6gb-verto-dual-fan" }, { "t": "hothardware.com — /news/nvidia-launches-6gb-geforce-rtx-3050", "u": "https://hothardware.com/news/nvidia-launches-6gb-geforce-rtx-3050" }, { "t": "en.wikipedia.org — /wiki/GeForce_30_series", "u": "https://en.wikipedia.org/wiki/GeForce_30_series" } ], "aka": null }, { "id": "rtx-4070-super", "name": "GeForce RTX 4070 SUPER", "short": "RTX 4070 SUPER", "seg": "geforce", "arch": "Ada", "archGroup": "Ada", "cls": "ada-geforce", "clsLabel": "Ada (GF)", "chip": "AD104", "date": "2024-01", "t": 2024.0, "status": null, "ff": null, "mem": 12.0, "memType": "GDDR6X", "bw": 504.0, "tdp": 220.0, "sms": 56.0, "tc": 224.0, "cuda": 7168.0, "boost": 2480.0, "v": { "fp32": [ 36.0, null, "p" ], "fp64": [ 0.5625, null, "d" ], "tf32": [ 35.5, 71.0, "d" ], "fp16": [ 71.0, 142.0, "d" ], "bf16": [ 71.0, 142.0, "d" ], "fp8": [ 142.0, 284.0, "d" ], "int8": [ 284.0, 568.0, "d" ], "int4": [ 568.0, 1136.0, "d" ], "fp8a16": [ 284.0, 568.0, "p" ], "fp16a16": [ 142.0, 284.0, "d" ] }, "how": { "fp32": "NVIDIA: “Shader Cores | Ada Lovelace | 36 TFLOPS” [nvidia.com]", "fp64": "Derived: FP32 ÷ 64 (this architecture's FP64 rate)", "tf32": "Derived from NVIDIA's headline figure, 568 TFLOPS FP8 with sparsity (so 284 dense). On GeForce Ada, TF32 runs at an eighth of the FP8 (FP16 accumulate) rate", "fp16": "Derived from NVIDIA's headline figure, 568 TFLOPS FP8 with sparsity (so 284 dense). On GeForce Ada, FP16 (FP32 accumulate) runs at a quarter of the FP8 (FP16 accumulate) rate", "bf16": "Derived from NVIDIA's headline figure, 568 TFLOPS FP8 with sparsity (so 284 dense). On GeForce Ada, BF16 runs at a quarter of the FP8 (FP16 accumulate) rate", "fp8": "Derived from NVIDIA's headline figure, 568 TFLOPS FP8 with sparsity (so 284 dense). On GeForce Ada, FP8 (FP32 accumulate) runs at half the FP8 (FP16 accumulate) rate", "int8": "Derived from NVIDIA's headline figure, 568 TFLOPS FP8 with sparsity (so 284 dense). On GeForce Ada, INT8 runs at the same rate as FP8 (FP16 accumulate)", "int4": "Derived from NVIDIA's headline figure, 568 TFLOPS FP8 with sparsity (so 284 dense). On GeForce Ada, INT4 runs at twice the FP8 (FP16 accumulate) rate", "fp8a16": "NVIDIA: “Tensor Cores (AI) | 4th Generation | 568 AI TOPS” (dense = half the sparse figure) [nvidia.com]", "fp16a16": "Derived from NVIDIA's headline figure, 568 TFLOPS FP8 with sparsity (so 284 dense). On GeForce Ada, FP16 (FP16 accumulate) runs at half the FP8 (FP16 accumulate) rate" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "fp6": "No FP6 tensor cores before Blackwell", "fp4": "No FP4 tensor cores before Blackwell" }, "headline": "“Tensor Cores (AI) | 4th Generation | 568 AI TOPS” — read as FP8, sparse", "anchor": "Derived from NVIDIA's headline figure, 568 TFLOPS FP8 with sparsity (so 284 dense). ", "notes": "No NVIDIA per-precision table. RT 82 TFLOPS.", "sources": [ { "t": "nvidia.com — /en-us/geforce/graphics-cards/40-series/rtx-4070-family/", "u": "https://www.nvidia.com/en-us/geforce/graphics-cards/40-series/rtx-4070-family/" }, { "t": "nvidia.com — /en-us/geforce/graphics-cards/compare/", "u": "https://www.nvidia.com/en-us/geforce/graphics-cards/compare/" }, { "t": "nvidianews.nvidia.com — /news/geforce-rtx-40-super-series", "u": "https://nvidianews.nvidia.com/news/geforce-rtx-40-super-series" }, { "t": "nvidia.com — /content/dam/en-zz/Solutions/geforce/news/geforce-rtx-4080-4070-ti-4070-super-gp", "u": "https://www.nvidia.com/content/dam/en-zz/Solutions/geforce/news/geforce-rtx-4080-4070-ti-4070-super-gpu/nvidia-geforce-rtx-ces-2024-4070-super-specifications.png" } ], "aka": null }, { "id": "rtx-4070-ti-super", "name": "GeForce RTX 4070 Ti SUPER", "short": "RTX 4070 Ti SUPER", "seg": "geforce", "arch": "Ada", "archGroup": "Ada", "cls": "ada-geforce", "clsLabel": "Ada (GF)", "chip": "AD103", "date": "2024-01", "t": 2024.0, "status": null, "ff": null, "mem": 16.0, "memType": "GDDR6X", "bw": 672.0, "tdp": 285.0, "sms": 66.0, "tc": 264.0, "cuda": 8448.0, "boost": 2610.0, "v": { "fp32": [ 44.0, null, "p" ], "fp64": [ 0.6875, null, "d" ], "tf32": [ 44.125, 88.25, "d" ], "fp16": [ 88.25, 176.5, "d" ], "bf16": [ 88.25, 176.5, "d" ], "fp8": [ 176.5, 353.0, "d" ], "int8": [ 353.0, 706.0, "d" ], "int4": [ 706.0, 1412.0, "d" ], "fp8a16": [ 353.0, 706.0, "p" ], "fp16a16": [ 176.5, 353.0, "d" ] }, "how": { "fp32": "NVIDIA: “Shader Cores | Ada Lovelace | 44 TFLOPS” [nvidia.com]", "fp64": "Derived: FP32 ÷ 64 (this architecture's FP64 rate)", "tf32": "Derived from NVIDIA's headline figure, 706 TFLOPS FP8 with sparsity (so 353 dense). On GeForce Ada, TF32 runs at an eighth of the FP8 (FP16 accumulate) rate", "fp16": "Derived from NVIDIA's headline figure, 706 TFLOPS FP8 with sparsity (so 353 dense). On GeForce Ada, FP16 (FP32 accumulate) runs at a quarter of the FP8 (FP16 accumulate) rate", "bf16": "Derived from NVIDIA's headline figure, 706 TFLOPS FP8 with sparsity (so 353 dense). On GeForce Ada, BF16 runs at a quarter of the FP8 (FP16 accumulate) rate", "fp8": "Derived from NVIDIA's headline figure, 706 TFLOPS FP8 with sparsity (so 353 dense). On GeForce Ada, FP8 (FP32 accumulate) runs at half the FP8 (FP16 accumulate) rate", "int8": "Derived from NVIDIA's headline figure, 706 TFLOPS FP8 with sparsity (so 353 dense). On GeForce Ada, INT8 runs at the same rate as FP8 (FP16 accumulate)", "int4": "Derived from NVIDIA's headline figure, 706 TFLOPS FP8 with sparsity (so 353 dense). On GeForce Ada, INT4 runs at twice the FP8 (FP16 accumulate) rate", "fp8a16": "NVIDIA: “Tensor Cores (AI) | 4th Generation | 706 AI TOPS” (dense = half the sparse figure) [nvidia.com]", "fp16a16": "Derived from NVIDIA's headline figure, 706 TFLOPS FP8 with sparsity (so 353 dense). On GeForce Ada, FP16 (FP16 accumulate) runs at half the FP8 (FP16 accumulate) rate" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "fp6": "No FP6 tensor cores before Blackwell", "fp4": "No FP4 tensor cores before Blackwell" }, "headline": "“Tensor Cores (AI) | 4th Generation | 706 AI TOPS” — read as FP8, sparse", "anchor": "Derived from NVIDIA's headline figure, 706 TFLOPS FP8 with sparsity (so 353 dense). ", "notes": "No NVIDIA per-precision table. RT 102 TFLOPS.", "sources": [ { "t": "nvidia.com — /en-us/geforce/graphics-cards/40-series/rtx-4070-family/", "u": "https://www.nvidia.com/en-us/geforce/graphics-cards/40-series/rtx-4070-family/" }, { "t": "nvidia.com — /en-us/geforce/graphics-cards/compare/", "u": "https://www.nvidia.com/en-us/geforce/graphics-cards/compare/" }, { "t": "nvidianews.nvidia.com — /news/geforce-rtx-40-super-series", "u": "https://nvidianews.nvidia.com/news/geforce-rtx-40-super-series" }, { "t": "nvidia.com — /content/dam/en-zz/Solutions/geforce/news/geforce-rtx-4080-4070-ti-4070-super-gp", "u": "https://www.nvidia.com/content/dam/en-zz/Solutions/geforce/news/geforce-rtx-4080-4070-ti-4070-super-gpu/nvidia-geforce-rtx-ces-2024-4070-ti-super-specifications.png" } ], "aka": null }, { "id": "rtx-4080-super", "name": "GeForce RTX 4080 SUPER", "short": "RTX 4080 SUPER", "seg": "geforce", "arch": "Ada", "archGroup": "Ada", "cls": "ada-geforce", "clsLabel": "Ada (GF)", "chip": "AD103", "date": "2024-01", "t": 2024.0, "status": null, "ff": null, "mem": 16.0, "memType": "GDDR6X", "bw": 736.0, "tdp": 320.0, "sms": 80.0, "tc": 320.0, "cuda": 10240.0, "boost": 2550.0, "v": { "fp32": [ 52.0, null, "p" ], "fp64": [ 0.8125, null, "d" ], "tf32": [ 52.25, 104.5, "d" ], "fp16": [ 104.5, 209.0, "d" ], "bf16": [ 104.5, 209.0, "d" ], "fp8": [ 209.0, 418.0, "d" ], "int8": [ 418.0, 836.0, "d" ], "int4": [ 836.0, 1672.0, "d" ], "fp8a16": [ 418.0, 836.0, "p" ], "fp16a16": [ 209.0, 418.0, "d" ] }, "how": { "fp32": "NVIDIA: “Shader Cores | Ada Lovelace | 52 TFLOPS” [nvidia.com]", "fp64": "Derived: FP32 ÷ 64 (this architecture's FP64 rate)", "tf32": "Derived from NVIDIA's headline figure, 836 TFLOPS FP8 with sparsity (so 418 dense). On GeForce Ada, TF32 runs at an eighth of the FP8 (FP16 accumulate) rate", "fp16": "Derived from NVIDIA's headline figure, 836 TFLOPS FP8 with sparsity (so 418 dense). On GeForce Ada, FP16 (FP32 accumulate) runs at a quarter of the FP8 (FP16 accumulate) rate", "bf16": "Derived from NVIDIA's headline figure, 836 TFLOPS FP8 with sparsity (so 418 dense). On GeForce Ada, BF16 runs at a quarter of the FP8 (FP16 accumulate) rate", "fp8": "Derived from NVIDIA's headline figure, 836 TFLOPS FP8 with sparsity (so 418 dense). On GeForce Ada, FP8 (FP32 accumulate) runs at half the FP8 (FP16 accumulate) rate", "int8": "Derived from NVIDIA's headline figure, 836 TFLOPS FP8 with sparsity (so 418 dense). On GeForce Ada, INT8 runs at the same rate as FP8 (FP16 accumulate)", "int4": "Derived from NVIDIA's headline figure, 836 TFLOPS FP8 with sparsity (so 418 dense). On GeForce Ada, INT4 runs at twice the FP8 (FP16 accumulate) rate", "fp8a16": "NVIDIA: “Tensor Cores (AI) | 4th Generation | 836 AI TOPS” (dense = half the sparse figure) [nvidia.com]", "fp16a16": "Derived from NVIDIA's headline figure, 836 TFLOPS FP8 with sparsity (so 418 dense). On GeForce Ada, FP16 (FP16 accumulate) runs at half the FP8 (FP16 accumulate) rate" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "fp6": "No FP6 tensor cores before Blackwell", "fp4": "No FP4 tensor cores before Blackwell" }, "headline": "“Tensor Cores (AI) | 4th Generation | 836 AI TOPS” — read as FP8, sparse", "anchor": "Derived from NVIDIA's headline figure, 836 TFLOPS FP8 with sparsity (so 418 dense). ", "notes": "No NVIDIA per-precision table. RT 121 TFLOPS.", "sources": [ { "t": "nvidia.com — /en-us/geforce/graphics-cards/40-series/rtx-4080-family/", "u": "https://www.nvidia.com/en-us/geforce/graphics-cards/40-series/rtx-4080-family/" }, { "t": "nvidia.com — /en-us/geforce/graphics-cards/compare/", "u": "https://www.nvidia.com/en-us/geforce/graphics-cards/compare/" }, { "t": "nvidianews.nvidia.com — /news/geforce-rtx-40-super-series", "u": "https://nvidianews.nvidia.com/news/geforce-rtx-40-super-series" }, { "t": "nvidia.com — /en-us/geforce/news/geforce-rtx-4080-4070-ti-4070-super-gpu/", "u": "https://www.nvidia.com/en-us/geforce/news/geforce-rtx-4080-4070-ti-4070-super-gpu/" }, { "t": "nvidia.com — /content/dam/en-zz/Solutions/geforce/news/geforce-rtx-4080-4070-ti-4070-super-gp", "u": "https://www.nvidia.com/content/dam/en-zz/Solutions/geforce/news/geforce-rtx-4080-4070-ti-4070-super-gpu/nvidia-geforce-rtx-ces-2024-4080-super-specifications.png" } ], "aka": null }, { "id": "rtx-4090-d", "name": "GeForce RTX 4090 D", "short": "RTX 4090 D", "seg": "geforce", "arch": "Ada", "archGroup": "Ada", "cls": "ada-geforce", "clsLabel": "Ada (GF)", "chip": "AD102", "date": "2023-12", "t": 2023.9166666666667, "status": null, "ff": null, "mem": 24.0, "memType": "GDDR6X", "bw": null, "tdp": 425.0, "sms": 114.0, "tc": 456.0, "cuda": 14592.0, "boost": 2520.0, "v": { "fp32": [ 74.0, null, "p" ], "fp64": [ 1.1562, null, "d" ], "tf32": [ 73.5625, 147.125, "d" ], "fp16": [ 147.125, 294.25, "d" ], "bf16": [ 147.125, 294.25, "d" ], "fp8": [ 294.25, 588.5, "d" ], "int8": [ 588.5, 1177.0, "d" ], "int4": [ 1177.0, 2354.0, "d" ], "fp8a16": [ 588.5, 1177.0, "p" ], "fp16a16": [ 294.25, 588.5, "d" ] }, "how": { "fp32": "NVIDIA: “Shader Core | Ada Lovelace | 74 TFLOPS” [nvidia.cn]", "fp64": "Derived: FP32 ÷ 64 (this architecture's FP64 rate)", "tf32": "Derived from NVIDIA's headline figure, 1,177 TFLOPS FP8 with sparsity (so 588.5 dense). On GeForce Ada, TF32 runs at an eighth of the FP8 (FP16 accumulate) rate", "fp16": "Derived from NVIDIA's headline figure, 1,177 TFLOPS FP8 with sparsity (so 588.5 dense). On GeForce Ada, FP16 (FP32 accumulate) runs at a quarter of the FP8 (FP16 accumulate) rate", "bf16": "Derived from NVIDIA's headline figure, 1,177 TFLOPS FP8 with sparsity (so 588.5 dense). On GeForce Ada, BF16 runs at a quarter of the FP8 (FP16 accumulate) rate", "fp8": "Derived from NVIDIA's headline figure, 1,177 TFLOPS FP8 with sparsity (so 588.5 dense). On GeForce Ada, FP8 (FP32 accumulate) runs at half the FP8 (FP16 accumulate) rate", "int8": "Derived from NVIDIA's headline figure, 1,177 TFLOPS FP8 with sparsity (so 588.5 dense). On GeForce Ada, INT8 runs at the same rate as FP8 (FP16 accumulate)", "int4": "Derived from NVIDIA's headline figure, 1,177 TFLOPS FP8 with sparsity (so 588.5 dense). On GeForce Ada, INT4 runs at twice the FP8 (FP16 accumulate) rate", "fp8a16": "NVIDIA: “Tensor Core | 第 4 代 | 1177 TOPS” (dense = half the sparse figure) [nvidia.cn]", "fp16a16": "Derived from NVIDIA's headline figure, 1,177 TFLOPS FP8 with sparsity (so 588.5 dense). On GeForce Ada, FP16 (FP16 accumulate) runs at half the FP8 (FP16 accumulate) rate" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "fp6": "No FP6 tensor cores before Blackwell", "fp4": "No FP4 tensor cores before Blackwell" }, "headline": "“Tensor Core | 第 4 代 | 1177 TOPS” — read as FP8, sparse", "anchor": "Derived from NVIDIA's headline figure, 1,177 TFLOPS FP8 with sparsity (so 588.5 dense). ", "notes": "China-only SKU. NVIDIA publishes no per-precision table for it. Consistency check only (not a published value): 1177 is what the RTX 4090's 1321 FP8-sparse figure scales to with 14592/16384 CUDA cores at the same 2.52 GHz boost. RT 170 TFLOPS on NVIDIA page.", "sources": [ { "t": "nvidia.cn — /geforce/graphics-cards/40-series/rtx-4090-d/", "u": "https://www.nvidia.cn/geforce/graphics-cards/40-series/rtx-4090-d/" }, { "t": "nvidia.cn — /geforce/graphics-cards/compare/", "u": "https://www.nvidia.cn/geforce/graphics-cards/compare/" }, { "t": "web.archive.org — /web/20231228142303/https://www.nvidia.cn/geforce/graphics-cards/40-series/rtx-4", "u": "https://web.archive.org/web/20231228142303/https://www.nvidia.cn/geforce/graphics-cards/40-series/rtx-4090-d/" } ], "aka": null }, { "id": "rtx-4060-ti-16gb", "name": "GeForce RTX 4060 Ti 16GB", "short": "RTX 4060 Ti 16GB", "seg": "geforce", "arch": "Ada", "archGroup": "Ada", "cls": "ada-geforce", "clsLabel": "Ada (GF)", "chip": "AD106", "date": "2023-07", "t": 2023.5, "status": null, "ff": null, "mem": 16.0, "memType": "GDDR6", "bw": 288.0, "tdp": 165.0, "sms": 34.0, "tc": 136.0, "cuda": 4352.0, "boost": 2540.0, "v": { "fp32": [ 22.0, null, "p" ], "fp64": [ 0.3438, null, "d" ], "tf32": [ 22.0625, 44.125, "d" ], "fp16": [ 44.125, 88.25, "d" ], "bf16": [ 44.125, 88.25, "d" ], "fp8": [ 88.25, 176.5, "d" ], "int8": [ 176.5, 353.0, "d" ], "int4": [ 353.0, 706.0, "d" ], "fp8a16": [ 176.5, 353.0, "p" ], "fp16a16": [ 88.25, 176.5, "d" ] }, "how": { "fp32": "NVIDIA: “Shader Cores | Ada Lovelace | 22 TFLOPS” [nvidia.com]", "fp64": "Derived: FP32 ÷ 64 (this architecture's FP64 rate)", "tf32": "Derived from NVIDIA's headline figure, 353 TFLOPS FP8 with sparsity (so 176.5 dense). On GeForce Ada, TF32 runs at an eighth of the FP8 (FP16 accumulate) rate", "fp16": "Derived from NVIDIA's headline figure, 353 TFLOPS FP8 with sparsity (so 176.5 dense). On GeForce Ada, FP16 (FP32 accumulate) runs at a quarter of the FP8 (FP16 accumulate) rate", "bf16": "Derived from NVIDIA's headline figure, 353 TFLOPS FP8 with sparsity (so 176.5 dense). On GeForce Ada, BF16 runs at a quarter of the FP8 (FP16 accumulate) rate", "fp8": "Derived from NVIDIA's headline figure, 353 TFLOPS FP8 with sparsity (so 176.5 dense). On GeForce Ada, FP8 (FP32 accumulate) runs at half the FP8 (FP16 accumulate) rate", "int8": "Derived from NVIDIA's headline figure, 353 TFLOPS FP8 with sparsity (so 176.5 dense). On GeForce Ada, INT8 runs at the same rate as FP8 (FP16 accumulate)", "int4": "Derived from NVIDIA's headline figure, 353 TFLOPS FP8 with sparsity (so 176.5 dense). On GeForce Ada, INT4 runs at twice the FP8 (FP16 accumulate) rate", "fp8a16": "NVIDIA: “Tensor Cores (AI) | 4th Generation | 353 AI TOPS” (dense = half the sparse figure) [nvidia.com]", "fp16a16": "Derived from NVIDIA's headline figure, 353 TFLOPS FP8 with sparsity (so 176.5 dense). On GeForce Ada, FP16 (FP16 accumulate) runs at half the FP8 (FP16 accumulate) rate" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "fp6": "No FP6 tensor cores before Blackwell", "fp4": "No FP4 tensor cores before Blackwell" }, "headline": "“Tensor Cores (AI) | 4th Generation | 353 AI TOPS” — read as FP8, sparse", "anchor": "Derived from NVIDIA's headline figure, 353 TFLOPS FP8 with sparsity (so 176.5 dense). ", "notes": "8 GB and 16 GB versions share all published compute specs; only memory size (and possibly TGP) differ. No NVIDIA per-precision table. RT 51 TFLOPS.", "sources": [ { "t": "nvidia.com — /en-us/geforce/graphics-cards/40-series/rtx-4060-4060ti/", "u": "https://www.nvidia.com/en-us/geforce/graphics-cards/40-series/rtx-4060-4060ti/" }, { "t": "nvidia.com — /en-us/geforce/graphics-cards/compare/", "u": "https://www.nvidia.com/en-us/geforce/graphics-cards/compare/" }, { "t": "nvidianews.nvidia.com — /news/geforce-rtx-4060-family-is-here-nvidias-revolutionary-ada-lovelace-archite", "u": "https://nvidianews.nvidia.com/news/geforce-rtx-4060-family-is-here-nvidias-revolutionary-ada-lovelace-architecture-comes-to-core-gamers-everywhere-starting-at-299" }, { "t": "nvidia.com — /en-us/geforce/news/geforce-rtx-4060-4060ti/", "u": "https://www.nvidia.com/en-us/geforce/news/geforce-rtx-4060-4060ti/" }, { "t": "nvidia.com — /content/dam/en-zz/Solutions/geforce/news/geforce-rtx-4060-4060ti/nvidia-geforce", "u": "https://www.nvidia.com/content/dam/en-zz/Solutions/geforce/news/geforce-rtx-4060-4060ti/nvidia-geforce-rtx-4060-ti-specifications-comparison.png" } ], "aka": null }, { "id": "rtx-4060", "name": "GeForce RTX 4060", "short": "RTX 4060", "seg": "geforce", "arch": "Ada", "archGroup": "Ada", "cls": "ada-geforce", "clsLabel": "Ada (GF)", "chip": "AD107", "date": "2023-06", "t": 2023.4166666666667, "status": null, "ff": null, "mem": 8.0, "memType": "GDDR6", "bw": 272.0, "tdp": 115.0, "sms": 24.0, "tc": 96.0, "cuda": 3072.0, "boost": 2460.0, "v": { "fp32": [ 15.0, null, "p" ], "fp64": [ 0.2344, null, "d" ], "tf32": [ 15.125, 30.25, "d" ], "fp16": [ 30.25, 60.5, "d" ], "bf16": [ 30.25, 60.5, "d" ], "fp8": [ 60.5, 121.0, "d" ], "int8": [ 121.0, 242.0, "d" ], "int4": [ 242.0, 484.0, "d" ], "fp8a16": [ 121.0, 242.0, "p" ], "fp16a16": [ 60.5, 121.0, "d" ] }, "how": { "fp32": "NVIDIA: “Shader Cores | Ada Lovelace | 15 TFLOPS” [nvidia.com]", "fp64": "Derived: FP32 ÷ 64 (this architecture's FP64 rate)", "tf32": "Derived from NVIDIA's headline figure, 242 TFLOPS FP8 with sparsity (so 121 dense). On GeForce Ada, TF32 runs at an eighth of the FP8 (FP16 accumulate) rate", "fp16": "Derived from NVIDIA's headline figure, 242 TFLOPS FP8 with sparsity (so 121 dense). On GeForce Ada, FP16 (FP32 accumulate) runs at a quarter of the FP8 (FP16 accumulate) rate", "bf16": "Derived from NVIDIA's headline figure, 242 TFLOPS FP8 with sparsity (so 121 dense). On GeForce Ada, BF16 runs at a quarter of the FP8 (FP16 accumulate) rate", "fp8": "Derived from NVIDIA's headline figure, 242 TFLOPS FP8 with sparsity (so 121 dense). On GeForce Ada, FP8 (FP32 accumulate) runs at half the FP8 (FP16 accumulate) rate", "int8": "Derived from NVIDIA's headline figure, 242 TFLOPS FP8 with sparsity (so 121 dense). On GeForce Ada, INT8 runs at the same rate as FP8 (FP16 accumulate)", "int4": "Derived from NVIDIA's headline figure, 242 TFLOPS FP8 with sparsity (so 121 dense). On GeForce Ada, INT4 runs at twice the FP8 (FP16 accumulate) rate", "fp8a16": "NVIDIA: “Tensor Cores (AI) | 4th Generation | 242 AI TOPS” (dense = half the sparse figure) [nvidia.com]", "fp16a16": "Derived from NVIDIA's headline figure, 242 TFLOPS FP8 with sparsity (so 121 dense). On GeForce Ada, FP16 (FP16 accumulate) runs at half the FP8 (FP16 accumulate) rate" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "fp6": "No FP6 tensor cores before Blackwell", "fp4": "No FP4 tensor cores before Blackwell" }, "headline": "“Tensor Cores (AI) | 4th Generation | 242 AI TOPS” — read as FP8, sparse", "anchor": "Derived from NVIDIA's headline figure, 242 TFLOPS FP8 with sparsity (so 121 dense). ", "notes": "No NVIDIA per-precision table. RT 35 TFLOPS.", "sources": [ { "t": "nvidia.com — /en-us/geforce/graphics-cards/40-series/rtx-4060-4060ti/", "u": "https://www.nvidia.com/en-us/geforce/graphics-cards/40-series/rtx-4060-4060ti/" }, { "t": "nvidia.com — /en-us/geforce/graphics-cards/compare/", "u": "https://www.nvidia.com/en-us/geforce/graphics-cards/compare/" }, { "t": "nvidia.com — /en-us/geforce/news/geforce-rtx-4060-available-june-29/", "u": "https://www.nvidia.com/en-us/geforce/news/geforce-rtx-4060-available-june-29/" }, { "t": "nvidia.com — /en-us/geforce/news/geforce-rtx-4060-4060ti/", "u": "https://www.nvidia.com/en-us/geforce/news/geforce-rtx-4060-4060ti/" }, { "t": "nvidia.com — /content/dam/en-zz/Solutions/geforce/news/geforce-rtx-4060-4060ti/nvidia-geforce", "u": "https://www.nvidia.com/content/dam/en-zz/Solutions/geforce/news/geforce-rtx-4060-4060ti/nvidia-geforce-rtx-4060-specifications-comparison.png" }, { "t": "nvidia.com — /content/dam/en-zz/Solutions/geforce/news/rtx-5060-desktop-family-laptop-5060-co", "u": "https://www.nvidia.com/content/dam/en-zz/Solutions/geforce/news/rtx-5060-desktop-family-laptop-5060-coming-soon/geforce-rtx-5060-desktop-family-specification-comparison.png" } ], "aka": null }, { "id": "rtx-4060-ti-8gb", "name": "GeForce RTX 4060 Ti 8GB", "short": "RTX 4060 Ti 8GB", "seg": "geforce", "arch": "Ada", "archGroup": "Ada", "cls": "ada-geforce", "clsLabel": "Ada (GF)", "chip": "AD106", "date": "2023-05", "t": 2023.3333333333333, "status": null, "ff": null, "mem": 8.0, "memType": "GDDR6", "bw": 288.0, "tdp": 160.0, "sms": 34.0, "tc": 136.0, "cuda": 4352.0, "boost": 2540.0, "v": { "fp32": [ 22.0, null, "p" ], "fp64": [ 0.3438, null, "d" ], "tf32": [ 22.0625, 44.125, "d" ], "fp16": [ 44.125, 88.25, "d" ], "bf16": [ 44.125, 88.25, "d" ], "fp8": [ 88.25, 176.5, "d" ], "int8": [ 176.5, 353.0, "d" ], "int4": [ 353.0, 706.0, "d" ], "fp8a16": [ 176.5, 353.0, "p" ], "fp16a16": [ 88.25, 176.5, "d" ] }, "how": { "fp32": "NVIDIA: “Shader Cores | Ada Lovelace | 22 TFLOPS” [nvidia.com]", "fp64": "Derived: FP32 ÷ 64 (this architecture's FP64 rate)", "tf32": "Derived from NVIDIA's headline figure, 353 TFLOPS FP8 with sparsity (so 176.5 dense). On GeForce Ada, TF32 runs at an eighth of the FP8 (FP16 accumulate) rate", "fp16": "Derived from NVIDIA's headline figure, 353 TFLOPS FP8 with sparsity (so 176.5 dense). On GeForce Ada, FP16 (FP32 accumulate) runs at a quarter of the FP8 (FP16 accumulate) rate", "bf16": "Derived from NVIDIA's headline figure, 353 TFLOPS FP8 with sparsity (so 176.5 dense). On GeForce Ada, BF16 runs at a quarter of the FP8 (FP16 accumulate) rate", "fp8": "Derived from NVIDIA's headline figure, 353 TFLOPS FP8 with sparsity (so 176.5 dense). On GeForce Ada, FP8 (FP32 accumulate) runs at half the FP8 (FP16 accumulate) rate", "int8": "Derived from NVIDIA's headline figure, 353 TFLOPS FP8 with sparsity (so 176.5 dense). On GeForce Ada, INT8 runs at the same rate as FP8 (FP16 accumulate)", "int4": "Derived from NVIDIA's headline figure, 353 TFLOPS FP8 with sparsity (so 176.5 dense). On GeForce Ada, INT4 runs at twice the FP8 (FP16 accumulate) rate", "fp8a16": "NVIDIA: “Tensor Cores (AI) | 4th Generation | 353 AI TOPS” (dense = half the sparse figure) [nvidia.com]", "fp16a16": "Derived from NVIDIA's headline figure, 353 TFLOPS FP8 with sparsity (so 176.5 dense). On GeForce Ada, FP16 (FP16 accumulate) runs at half the FP8 (FP16 accumulate) rate" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "fp6": "No FP6 tensor cores before Blackwell", "fp4": "No FP4 tensor cores before Blackwell" }, "headline": "“Tensor Cores (AI) | 4th Generation | 353 AI TOPS” — read as FP8, sparse", "anchor": "Derived from NVIDIA's headline figure, 353 TFLOPS FP8 with sparsity (so 176.5 dense). ", "notes": "8 GB and 16 GB versions share all published compute specs; only memory size (and possibly TGP) differ. No NVIDIA per-precision table. RT 51 TFLOPS.", "sources": [ { "t": "nvidia.com — /en-us/geforce/graphics-cards/40-series/rtx-4060-4060ti/", "u": "https://www.nvidia.com/en-us/geforce/graphics-cards/40-series/rtx-4060-4060ti/" }, { "t": "nvidia.com — /en-us/geforce/graphics-cards/compare/", "u": "https://www.nvidia.com/en-us/geforce/graphics-cards/compare/" }, { "t": "nvidianews.nvidia.com — /news/geforce-rtx-4060-family-is-here-nvidias-revolutionary-ada-lovelace-archite", "u": "https://nvidianews.nvidia.com/news/geforce-rtx-4060-family-is-here-nvidias-revolutionary-ada-lovelace-architecture-comes-to-core-gamers-everywhere-starting-at-299" }, { "t": "nvidia.com — /en-us/geforce/news/geforce-rtx-4060-4060ti/", "u": "https://www.nvidia.com/en-us/geforce/news/geforce-rtx-4060-4060ti/" }, { "t": "nvidia.com — /content/dam/en-zz/Solutions/geforce/news/geforce-rtx-4060-4060ti/nvidia-geforce", "u": "https://www.nvidia.com/content/dam/en-zz/Solutions/geforce/news/geforce-rtx-4060-4060ti/nvidia-geforce-rtx-4060-ti-specifications-comparison.png" } ], "aka": null }, { "id": "rtx-4070", "name": "GeForce RTX 4070", "short": "RTX 4070", "seg": "geforce", "arch": "Ada", "archGroup": "Ada", "cls": "ada-geforce", "clsLabel": "Ada (GF)", "chip": "AD104", "date": "2023-04", "t": 2023.25, "status": null, "ff": null, "mem": 12.0, "memType": "GDDR6X", "bw": 504.0, "tdp": 200.0, "sms": 46.0, "tc": 184.0, "cuda": 5888.0, "boost": 2475.0, "v": { "fp32": [ 29.1, null, "p" ], "fp64": [ 0.4547, null, "d" ], "tf32": [ 29.1, 58.2, "p" ], "fp16": [ 58.3, 116.6, "p" ], "bf16": [ 58.3, 116.6, "p" ], "fp8": [ 116.6, 233.2, "p" ], "int8": [ 233.2, 466.4, "p" ], "int4": [ 466.4, 932.8, "d" ], "fp8a16": [ 233.2, 466.4, "p" ], "fp16a16": [ 116.6, 233.2, "p" ] }, "how": { "fp32": "NVIDIA: “Peak FP32 TFLOPS (non-Tensor)^1 | 29.1” [images.nvidia.com]", "fp64": "Derived: FP32 ÷ 64 (this architecture's FP64 rate)", "tf32": "NVIDIA: “Peak TF32 Tensor TFLOPS^1 | 29.1/58.2^2” [images.nvidia.com]", "fp16": "NVIDIA: “Peak FP16 Tensor TFLOPS with FP32 Accumulate^1 | 58.3/116.6^2” [images.nvidia.com]", "bf16": "NVIDIA: “Peak BF16 Tensor TFLOPS with FP32 Accumulate^1 | 58.3/116.6^2” [images.nvidia.com]", "fp8": "NVIDIA: “Peak FP8 Tensor TFLOPS with FP32 Accumulate^1 | 116.6/233.2^2” [images.nvidia.com]", "int8": "NVIDIA: “Peak INT8 Tensor TOPS^1 | 233.2/466.4^2” [images.nvidia.com]", "int4": "Derived from NVIDIA's published FP16 (FP16 accumulate) figure of 116.6 dense. On GeForce Ada, INT4 runs at 4× the FP16 (FP16 accumulate) rate", "fp8a16": "NVIDIA: “Peak FP8 Tensor TFLOPS with FP16 Accumulate^1 | 233.2/466.4^2” [images.nvidia.com]", "fp16a16": "NVIDIA: “Peak FP16 Tensor TFLOPS with FP16 Accumulate^1 | 116.6/233.2^2” [images.nvidia.com]" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "fp6": "No FP6 tensor cores before Blackwell", "fp4": "No FP4 tensor cores before Blackwell" }, "headline": "“Tensor Cores (AI) | 4th Generation | 466 AI TOPS” — read as FP8, sparse", "anchor": "Derived from NVIDIA's published FP16 (FP16 accumulate) figure of 116.6 dense. ", "notes": "Only NVIDIA per-precision source is the RTX 4070 column of RTX Blackwell whitepaper V1.1 Table 6 (no INT4 row). Memory/bandwidth figures are for the GDDR6X version; NVIDIA lists a 12 GB GDDR6 version too but its data rate/bandwidth is not on the NVIDIA pages reviewed. Product page: Shader 29 TFLOPS, RT 67 TFLOPS.", "sources": [ { "t": "images.nvidia.com — /aem-dam/Solutions/geforce/blackwell/nvidia-rtx-blackwell-gpu-architecture.pdf", "u": "https://images.nvidia.com/aem-dam/Solutions/geforce/blackwell/nvidia-rtx-blackwell-gpu-architecture.pdf" }, { "t": "nvidia.com — /en-us/geforce/graphics-cards/40-series/rtx-4070-family/", "u": "https://www.nvidia.com/en-us/geforce/graphics-cards/40-series/rtx-4070-family/" }, { "t": "nvidia.com — /en-us/geforce/graphics-cards/compare/", "u": "https://www.nvidia.com/en-us/geforce/graphics-cards/compare/" }, { "t": "nvidianews.nvidia.com — /news/nvidia-geforce-rtx-4070-brings-power-of-ada-lovelace-architecture-and-dlss", "u": "https://nvidianews.nvidia.com/news/nvidia-geforce-rtx-4070-brings-power-of-ada-lovelace-architecture-and-dlss-3-to-millions-more-gamers-and-creators-starting-at-599" } ], "aka": null }, { "id": "rtx-4070-ti", "name": "GeForce RTX 4070 Ti", "short": "RTX 4070 Ti", "seg": "geforce", "arch": "Ada", "archGroup": "Ada", "cls": "ada-geforce", "clsLabel": "Ada (GF)", "chip": "AD104", "date": "2023-01", "t": 2023.0, "status": null, "ff": null, "mem": 12.0, "memType": "GDDR6X", "bw": 504.0, "tdp": 285.0, "sms": 60.0, "tc": 240.0, "cuda": 7680.0, "boost": 2610.0, "v": { "fp32": [ 40.1, null, "p" ], "fp64": [ 0.6266, null, "d" ], "tf32": [ 40.1, 80.2, "p" ], "fp16": [ 80.2, 160.4, "p" ], "bf16": [ 80.2, 160.4, "p" ], "fp8": [ 160.4, 320.8, "p" ], "int8": [ 320.7, 641.4, "p" ], "int4": [ 641.6, 1283.2, "d" ], "fp8a16": [ 320.7, 641.4, "p" ], "fp16a16": [ 160.4, 320.8, "p" ] }, "how": { "fp32": "NVIDIA: “Peak FP32 TFLOPS (non-Tensor)^1 | 40.1” [images.nvidia.com]", "fp64": "Derived: FP32 ÷ 64 (this architecture's FP64 rate)", "tf32": "NVIDIA: “Peak TF32 Tensor TFLOPS^1 | 40.1/80.2^2” [images.nvidia.com]", "fp16": "NVIDIA: “Peak FP16 Tensor TFLOPS with FP32 Accumulate^1 | 80.2/160.4^2” [images.nvidia.com]", "bf16": "NVIDIA: “Peak BF16 Tensor TFLOPS with FP32 Accumulate^1 | 80.2/160.4^2” [images.nvidia.com]", "fp8": "NVIDIA: “Peak FP8 Tensor TFLOPS with FP32 Accumulate^1 | 160.4/320.8^2” [images.nvidia.com]", "int8": "NVIDIA: “Peak INT8 Tensor TOPS^1 | 320.7/641.4^2” [images.nvidia.com]", "int4": "Derived from NVIDIA's published FP16 (FP16 accumulate) figure of 160.4 dense. On GeForce Ada, INT4 runs at 4× the FP16 (FP16 accumulate) rate", "fp8a16": "NVIDIA: “Peak FP8 Tensor TFLOPS with FP16 Accumulate^1 | 320.7/641.4^2” [images.nvidia.com]", "fp16a16": "NVIDIA: “Peak FP16 Tensor TFLOPS with FP16 Accumulate^1 | 160.4/320.8^2” [images.nvidia.com]" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "fp6": "No FP6 tensor cores before Blackwell", "fp4": "No FP4 tensor cores before Blackwell" }, "headline": "“Tensor Cores (AI) | 4th Generation | 641 AI TOPS” — read as FP8, sparse", "anchor": "Derived from NVIDIA's published FP16 (FP16 accumulate) figure of 160.4 dense. ", "notes": "Only NVIDIA per-precision source is the RTX 4070 Ti comparison column of the RTX Blackwell whitepaper V1.1 Table 5 (the Ada whitepaper has no AD104 table). That table has no INT4 row, so INT4 is unpublished. Product page: Shader 40 TFLOPS, RT 93 TFLOPS.", "sources": [ { "t": "images.nvidia.com — /aem-dam/Solutions/geforce/blackwell/nvidia-rtx-blackwell-gpu-architecture.pdf", "u": "https://images.nvidia.com/aem-dam/Solutions/geforce/blackwell/nvidia-rtx-blackwell-gpu-architecture.pdf" }, { "t": "nvidia.com — /en-us/geforce/graphics-cards/40-series/rtx-4070-family/", "u": "https://www.nvidia.com/en-us/geforce/graphics-cards/40-series/rtx-4070-family/" }, { "t": "nvidia.com — /en-us/geforce/graphics-cards/compare/", "u": "https://www.nvidia.com/en-us/geforce/graphics-cards/compare/" }, { "t": "nvidia.com — /en-us/geforce/news/geforce-rtx-4070-ti/", "u": "https://www.nvidia.com/en-us/geforce/news/geforce-rtx-4070-ti/" } ], "aka": null }, { "id": "rtx-4080", "name": "GeForce RTX 4080", "short": "RTX 4080", "seg": "geforce", "arch": "Ada", "archGroup": "Ada", "cls": "ada-geforce", "clsLabel": "Ada (GF)", "chip": "AD103", "date": "2022-11", "t": 2022.8333333333333, "status": null, "ff": null, "mem": 16.0, "memType": "GDDR6X", "bw": 716.8, "tdp": 320.0, "sms": 76.0, "tc": 304.0, "cuda": 9728.0, "boost": 2505.0, "v": { "fp32": [ 48.7, null, "p" ], "fp64": [ 0.7609, null, "d" ], "tf32": [ 48.7, 97.4, "p" ], "fp16": [ 97.5, 195.0, "p" ], "bf16": [ 97.5, 195.0, "p" ], "fp8": [ 194.9, 389.8, "p" ], "int8": [ 389.9, 779.82, "p" ], "int4": [ 779.8, 1559.6, "p" ], "fp8a16": [ 389.9, 779.8, "p" ], "fp16a16": [ 194.9, 389.8, "p" ] }, "how": { "fp32": "NVIDIA: “Peak FP32 TFLOPS (non-Tensor)^1 | 48.7” [images.nvidia.com]", "fp64": "Derived: FP32 ÷ 64 (this architecture's FP64 rate)", "tf32": "NVIDIA: “Peak TF32 Tensor TFLOPS^1 | 48.7/97.4^2” [images.nvidia.com]", "fp16": "NVIDIA: “Peak FP16 Tensor TFLOPS with FP32 Accumulate^1 | 97.5/195^2” [images.nvidia.com]", "bf16": "NVIDIA: “Peak BF16 Tensor TFLOPS with FP32 Accumulate^1 | 97.5/195^2” [images.nvidia.com]", "fp8": "NVIDIA: “Peak FP8 Tensor TFLOPS with FP32 Accumulate^1 | 194.9/389.8^2,4” [images.nvidia.com]", "int8": "NVIDIA: “Peak INT8 Tensor TOPS^1 | 389.9/779.82^2” [images.nvidia.com]", "int4": "NVIDIA: “Peak INT4 Tensor TOPS^1 | 779.8/1559.6^2” [images.nvidia.com]", "fp8a16": "NVIDIA: “Peak FP8 Tensor TFLOPS with FP16 Accumulate^1 | 389.9/779.8^2” [images.nvidia.com]", "fp16a16": "NVIDIA: “Peak FP16 Tensor TFLOPS with FP16 Accumulate^1 | 194.9/389.8^2” [images.nvidia.com]" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "fp6": "No FP6 tensor cores before Blackwell", "fp4": "No FP4 tensor cores before Blackwell" }, "headline": "“Tensor Cores (AI) | 4th Generation | 780 AI TOPS” — read as FP8, sparse", "anchor": "Derived from NVIDIA's published FP16 (FP16 accumulate) figure of 194.9 dense. ", "notes": "Ada whitepaper calls it 'RTX 4080 16 GB' (Appendix B Table 3). RTX Blackwell whitepaper Table 4 reprints identical values (including the INT8 '779.82'). Product page: Shader 49 TFLOPS, RT 113 TFLOPS.", "sources": [ { "t": "images.nvidia.com — /aem-dam/Solutions/geforce/ada/nvidia-ada-gpu-architecture.pdf", "u": "https://images.nvidia.com/aem-dam/Solutions/geforce/ada/nvidia-ada-gpu-architecture.pdf" }, { "t": "images.nvidia.com — /aem-dam/Solutions/geforce/blackwell/nvidia-rtx-blackwell-gpu-architecture.pdf", "u": "https://images.nvidia.com/aem-dam/Solutions/geforce/blackwell/nvidia-rtx-blackwell-gpu-architecture.pdf" }, { "t": "nvidia.com — /en-us/geforce/graphics-cards/40-series/rtx-4080-family/", "u": "https://www.nvidia.com/en-us/geforce/graphics-cards/40-series/rtx-4080-family/" }, { "t": "nvidia.com — /en-us/geforce/graphics-cards/compare/", "u": "https://www.nvidia.com/en-us/geforce/graphics-cards/compare/" }, { "t": "nvidia.com — /en-us/geforce/news/geforce-rtx-4080-out-now/", "u": "https://www.nvidia.com/en-us/geforce/news/geforce-rtx-4080-out-now/" }, { "t": "nvidianews.nvidia.com — /news/nvidia-delivers-quantum-leap-in-performance-introduces-new-era-of-neural-r", "u": "https://nvidianews.nvidia.com/news/nvidia-delivers-quantum-leap-in-performance-introduces-new-era-of-neural-rendering-with-geforce-rtx-40-series" } ], "aka": null }, { "id": "rtx-3060-8gb", "name": "GeForce RTX 3060 8GB", "short": "RTX 3060 8GB", "seg": "geforce", "arch": "Ampere", "archGroup": "Ampere", "cls": "ampere-geforce", "clsLabel": "Ampere GA10x (GF)", "chip": "GA106", "date": "2022-10", "t": 2022.75, "status": null, "ff": "desktop PCIe card", "mem": 8.0, "memType": "GDDR6", "bw": null, "tdp": 170.0, "sms": 28.0, "tc": 112.0, "cuda": 3584.0, "boost": 1780.0, "v": { "fp32": [ 12.759, null, "d" ], "fp64": [ 0.1994, null, "d" ], "tf32": [ 12.759, 25.5181, "d" ], "fp16": [ 25.5181, 51.0362, "d" ], "bf16": [ 25.5181, 51.0362, "d" ], "int8": [ 102.0723, 204.1446, "d" ], "int4": [ 204.1446, 408.2893, "d" ], "fp16a16": [ 51.0362, 102.0723, "d" ] }, "how": { "fp32": "Derived: 2 × 3,584 CUDA cores × 1,780 MHz boost clock", "fp64": "Derived: FP32 ÷ 64 (this architecture's FP64 rate)", "tf32": "Derived: 28 SMs × 1,780 MHz boost clock × 256 TF32 ops per clock per SM on GeForce Ampere. NVIDIA publishes no tensor figure for this card", "fp16": "Derived: 28 SMs × 1,780 MHz boost clock × 512 FP16 (FP32 accumulate) ops per clock per SM on GeForce Ampere. NVIDIA publishes no tensor figure for this card", "bf16": "Derived: 28 SMs × 1,780 MHz boost clock × 512 BF16 ops per clock per SM on GeForce Ampere. NVIDIA publishes no tensor figure for this card", "int8": "Derived: 28 SMs × 1,780 MHz boost clock × 2,048 INT8 ops per clock per SM on GeForce Ampere. NVIDIA publishes no tensor figure for this card", "int4": "Derived: 28 SMs × 1,780 MHz boost clock × 4,096 INT4 ops per clock per SM on GeForce Ampere. NVIDIA publishes no tensor figure for this card", "fp16a16": "Derived: 28 SMs × 1,780 MHz boost clock × 1,024 FP16 (FP16 accumulate) ops per clock per SM on GeForce Ampere. NVIDIA publishes no tensor figure for this card" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "fp8": "No FP8 tensor cores before Ada/Hopper (FP8 models run at FP16 speed)", "fp6": "No FP6 tensor cores before Blackwell", "fp4": "No FP4 tensor cores before Blackwell" }, "headline": null, "anchor": "Derived from 28 SMs × 1,780 MHz boost clock. ", "notes": "NVIDIA published no throughput figure and made no announcement. The 8GB model shares the RTX 3060 column of NVIDIA's spec page, so the 170 W figure applies to both. Bandwidth left null. CONFLICT: PNY's page prints 'Memory Bandwidth (GB/sec) 360' next to 128-bit / 15 Gbps. 360 GB/s is the 12GB/192-bit figure, so the page looks copy-pasted. The secondary sources also disagree: Guru3D reports 240 GB/s at 15 Gbps, while Wikipedia's row lists 224 GB/s next to a 15 Gbps memory clock. NVIDIA prints no bandwidth.", "sources": [ { "t": "nvidia.com — /en-us/geforce/graphics-cards/30-series/rtx-3060-3060ti/", "u": "https://www.nvidia.com/en-us/geforce/graphics-cards/30-series/rtx-3060-3060ti/" }, { "t": "pny.com — /pny-geforce-rtx-3060-8gb-verto-dual-fan", "u": "https://www.pny.com/pny-geforce-rtx-3060-8gb-verto-dual-fan" }, { "t": "guru3d.com — /news-story/geforce-rtx-3060-with-8gb-128-bit-memory-bus-memory-released.html", "u": "https://www.guru3d.com/news-story/geforce-rtx-3060-with-8gb-128-bit-memory-bus-memory-released.html" }, { "t": "en.wikipedia.org — /wiki/GeForce_30_series", "u": "https://en.wikipedia.org/wiki/GeForce_30_series" } ], "aka": null }, { "id": "rtx-4090", "name": "GeForce RTX 4090", "short": "RTX 4090", "seg": "geforce", "arch": "Ada", "archGroup": "Ada", "cls": "ada-geforce", "clsLabel": "Ada (GF)", "chip": "AD102", "date": "2022-10", "t": 2022.75, "status": null, "ff": null, "mem": 24.0, "memType": "GDDR6X", "bw": 1008.0, "tdp": 450.0, "sms": 128.0, "tc": 512.0, "cuda": 16384.0, "boost": 2520.0, "v": { "fp32": [ 82.6, null, "p" ], "fp64": [ 1.2906, null, "d" ], "tf32": [ 82.6, 165.2, "p" ], "fp16": [ 165.2, 330.4, "p" ], "bf16": [ 165.2, 330.4, "p" ], "fp8": [ 330.3, 660.6, "p" ], "int8": [ 660.6, 1321.2, "p" ], "int4": [ 1321.2, 2642.4, "p" ], "fp8a16": [ 660.6, 1321.2, "p" ], "fp16a16": [ 330.3, 660.6, "p" ] }, "how": { "fp32": "NVIDIA: “Peak FP32 TFLOPS (non-Tensor)^1 | 82.6” [images.nvidia.com]", "fp64": "Derived: FP32 ÷ 64 (this architecture's FP64 rate)", "tf32": "NVIDIA: “Peak TF32 Tensor TFLOPS^1 | 82.6/165.2^2” [images.nvidia.com]", "fp16": "NVIDIA: “Peak FP16 Tensor TFLOPS with FP32 Accumulate^1 | 165.2/330.4^2” [images.nvidia.com]", "bf16": "NVIDIA: “Peak BF16 Tensor TFLOPS with FP32 Accumulate^1 | 165.2/330.4^2” [images.nvidia.com]", "fp8": "NVIDIA: “Peak FP8 Tensor TFLOPS with FP32 Accumulate^1 | 330.3/660.6^2,4” [images.nvidia.com]", "int8": "NVIDIA: “Peak INT8 Tensor TOPS^1 | 660.6/1321.2^2” [images.nvidia.com]", "int4": "NVIDIA: “Peak INT4 Tensor TOPS^1 | 1321.2/2642.4^2” [images.nvidia.com]", "fp8a16": "NVIDIA: “Peak FP8 Tensor TFLOPS with FP16 Accumulate^1 | 660.6/1321.2^2” [images.nvidia.com]", "fp16a16": "NVIDIA: “Peak FP16 Tensor TFLOPS with FP16 Accumulate^1 | 330.3/660.6^2” [images.nvidia.com]" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "fp6": "No FP6 tensor cores before Blackwell", "fp4": "No FP4 tensor cores before Blackwell" }, "headline": "“Tensor Cores (AI) | 4th Generation | 1321 AI TOPS” — read as FP8, sparse", "anchor": "Derived from NVIDIA's published FP16 (FP16 accumulate) figure of 330.3 dense. ", "notes": "Ada whitepaper V2.02 Appendix A Table 2 is the per-precision source; RTX Blackwell whitepaper V1.1 Table 3 reprints identical RTX 4090 values. GeForce half-rate pattern as printed: FP16 FP32-acc / BF16 (165.2) = half of FP16 FP16-acc (330.3); FP8 FP32-acc (330.3) = half of FP8 FP16-acc (660.6); TF32 82.6. Whitepaper: 'The FP64 TFLOP rate is 1/64th the TFLOP rate of FP32 operations' (AD102, 288 FP64 cores) - no absolute FP64 number published. Product page: Shader 83 TFLOPS, RT 191 TFLOPS. Non-tensor FP16/BF16 82.6 and INT32 41.3 TOPS are in architecture_tables.", "sources": [ { "t": "images.nvidia.com — /aem-dam/Solutions/geforce/ada/nvidia-ada-gpu-architecture.pdf", "u": "https://images.nvidia.com/aem-dam/Solutions/geforce/ada/nvidia-ada-gpu-architecture.pdf" }, { "t": "images.nvidia.com — /aem-dam/Solutions/geforce/blackwell/nvidia-rtx-blackwell-gpu-architecture.pdf", "u": "https://images.nvidia.com/aem-dam/Solutions/geforce/blackwell/nvidia-rtx-blackwell-gpu-architecture.pdf" }, { "t": "nvidia.com — /en-us/geforce/graphics-cards/40-series/rtx-4090/", "u": "https://www.nvidia.com/en-us/geforce/graphics-cards/40-series/rtx-4090/" }, { "t": "nvidia.com — /en-us/geforce/graphics-cards/compare/", "u": "https://www.nvidia.com/en-us/geforce/graphics-cards/compare/" }, { "t": "nvidianews.nvidia.com — /news/nvidia-delivers-quantum-leap-in-performance-introduces-new-era-of-neural-r", "u": "https://nvidianews.nvidia.com/news/nvidia-delivers-quantum-leap-in-performance-introduces-new-era-of-neural-rendering-with-geforce-rtx-40-series" } ], "aka": null }, { "id": "rtx-3090-ti", "name": "GeForce RTX 3090 Ti", "short": "RTX 3090 Ti", "seg": "geforce", "arch": "Ampere", "archGroup": "Ampere", "cls": "ampere-geforce", "clsLabel": "Ampere GA10x (GF)", "chip": "GA102", "date": "2022-03", "t": 2022.1666666666667, "status": null, "ff": "3-slot desktop PCIe card (Founders Edition)", "mem": 24.0, "memType": "GDDR6X", "bw": 1008.0, "tdp": 450.0, "sms": 84.0, "tc": 336.0, "cuda": 10752.0, "boost": 1860.0, "v": { "fp32": [ 40.0, null, "p" ], "fp64": [ 0.625, null, "d" ], "tf32": [ 40.0, 80.0, "p" ], "fp16": [ 80.0, 160.0, "p" ], "bf16": [ 80.0, 160.0, "p" ], "int8": [ 320.0, 640.0, "p" ], "int4": [ 640.0, 1280.0, "p" ], "fp16a16": [ 160.0, 320.0, "p" ] }, "how": { "fp32": "NVIDIA: “Table 2: Peak FP32 TFLOPS (non-Tensor) 40” [images.nvidia.com]", "fp64": "Derived: FP32 ÷ 64 (this architecture's FP64 rate)", "tf32": "NVIDIA: “Table 2: Peak TF32 Tensor TFLOPS 40/80” [images.nvidia.com]", "fp16": "NVIDIA: “Table 2: Peak FP16 Tensor TFLOPS with FP32 Accumulate 80/160” [images.nvidia.com]", "bf16": "NVIDIA: “Table 2: Peak BF16 Tensor TFLOPS with FP32 Accumulate 80/160” [images.nvidia.com]", "int8": "NVIDIA: “Table 2: Peak INT8 Tensor TOPS 320/640” [images.nvidia.com]", "int4": "NVIDIA: “Table 2: Peak INT4 Tensor TOPS 640/1280” [images.nvidia.com]", "fp16a16": "NVIDIA: “Table 2: Peak FP16 Tensor TFLOPS with FP16 Accumulate 160/320” [images.nvidia.com]" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "fp8": "No FP8 tensor cores before Ada/Hopper (FP8 models run at FP16 speed)", "fp6": "No FP6 tensor cores before Blackwell", "fp4": "No FP4 tensor cores before Blackwell" }, "headline": "“the GeForce RTX 3090 Ti features a record-breaking 10,752 CUDA cores, and boasts 78 RT-TFLOPs, 40 Shader-TFLOPs and 320 Tensor-TFLOPs of power”", "anchor": "Derived from NVIDIA's published FP16 (FP16 accumulate) figure of 160 dense. ", "notes": "Per-precision table from Ada whitepaper v2.02 Appendix A, Table 2 'GeForce RTX 4090 vs RTX 3090 Ti vs 2080 Ti' (also summarized in Table 1). The GA102 whitepaper predates this card. The GeForce news article also says '24GB of the fastest 21Gbps GDDR6X memory'. FP8 rows are 'N/A' for the 3090 Ti. GeForce half-rate pattern visible (160 vs 80; TF32 40).", "sources": [ { "t": "images.nvidia.com — /aem-dam/Solutions/geforce/ada/nvidia-ada-gpu-architecture.pdf", "u": "https://images.nvidia.com/aem-dam/Solutions/geforce/ada/nvidia-ada-gpu-architecture.pdf" }, { "t": "nvidia.com — /en-us/geforce/graphics-cards/30-series/rtx-3090-3090ti/", "u": "https://www.nvidia.com/en-us/geforce/graphics-cards/30-series/rtx-3090-3090ti/" }, { "t": "nvidia.com — /en-us/geforce/news/geforce-rtx-3090-ti-out-now/", "u": "https://www.nvidia.com/en-us/geforce/news/geforce-rtx-3090-ti-out-now/" } ], "aka": null }, { "id": "rtx-3050-8gb", "name": "GeForce RTX 3050 8GB", "short": "RTX 3050 8GB", "seg": "geforce", "arch": "Ampere", "archGroup": "Ampere", "cls": "ampere-geforce", "clsLabel": "Ampere GA10x (GF)", "chip": "GA106", "date": "2022-01", "t": 2022.0, "status": null, "ff": "desktop PCIe card", "mem": 8.0, "memType": "GDDR6", "bw": 224.0, "tdp": 130.0, "sms": 20.0, "tc": 80.0, "cuda": 2560.0, "boost": 1780.0, "v": { "fp32": [ 9.0, null, "p" ], "fp64": [ 0.1406, null, "d" ], "tf32": [ 9.125, 18.25, "d" ], "fp16": [ 18.25, 36.5, "d" ], "bf16": [ 18.25, 36.5, "d" ], "int8": [ 73.0, 146.0, "d" ], "int4": [ 146.0, 292.0, "d" ], "fp16a16": [ 36.5, 73.0, "p" ] }, "how": { "fp32": "NVIDIA: “GEFORCE RTX 3050 Step Up to RTX: 9 Shader-TFLOPS, 18 RT-TFLOPS, 73 Tensor-TFLOPS, 8 GB G6, Starting at $249, Available Jan. 27” [images.nvidia.com]", "fp64": "Derived: FP32 ÷ 64 (this architecture's FP64 rate)", "tf32": "Derived from NVIDIA's headline figure, 73 TFLOPS FP16 with sparsity (so 36.5 dense). On GeForce Ampere, TF32 runs at a quarter of the FP16 (FP16 accumulate) rate", "fp16": "Derived from NVIDIA's headline figure, 73 TFLOPS FP16 with sparsity (so 36.5 dense). On GeForce Ampere, FP16 (FP32 accumulate) runs at half the FP16 (FP16 accumulate) rate", "bf16": "Derived from NVIDIA's headline figure, 73 TFLOPS FP16 with sparsity (so 36.5 dense). On GeForce Ampere, BF16 runs at half the FP16 (FP16 accumulate) rate", "int8": "Derived from NVIDIA's headline figure, 73 TFLOPS FP16 with sparsity (so 36.5 dense). On GeForce Ampere, INT8 runs at twice the FP16 (FP16 accumulate) rate", "int4": "Derived from NVIDIA's headline figure, 73 TFLOPS FP16 with sparsity (so 36.5 dense). On GeForce Ampere, INT4 runs at 4× the FP16 (FP16 accumulate) rate", "fp16a16": "NVIDIA: “73 Tensor-TFLOPS” (precision not stated; GeForce Ampere headline figures are FP16) (sparsity not stated; NVIDIA's headline figures include it from Ampere on, and the card's clock confirms it) (dense = half the sparse figure) [images.nvidia.com]" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "fp8": "No FP8 tensor cores before Ada/Hopper (FP8 models run at FP16 speed)", "fp6": "No FP6 tensor cores before Blackwell", "fp4": "No FP4 tensor cores before Blackwell" }, "headline": "“73 Tensor-TFLOPS”", "anchor": "Derived from NVIDIA's headline figure, 73 TFLOPS FP16 with sparsity (so 36.5 dense). ", "notes": "Throughput figures appear only in a CES 2022 slide image embedded in NVIDIA's GeForce news article (Jan 4, 2022). The article text has no TFLOPS. NVIDIA page footnote: 'GeForce RTX 3050 (OEM) has 2304 CUDA Cores, a Base Clock of 1.51 GHz, and a Boost Clock of 1.76 GHz'. Per Wikipedia, a GA107-based 8GB variant (115 W) followed in Dec 2022; NVIDIA's page still lists 130 W. Reference-clocked PNY board boost: 1777 MHz. No Founders Edition.", "sources": [ { "t": "nvidia.com — /en-us/geforce/graphics-cards/30-series/rtx-3050/", "u": "https://www.nvidia.com/en-us/geforce/graphics-cards/30-series/rtx-3050/" }, { "t": "nvidia.com — /en-us/geforce/news/geforce-rtx-3050-graphics-cards/", "u": "https://www.nvidia.com/en-us/geforce/news/geforce-rtx-3050-graphics-cards/" }, { "t": "images.nvidia.com — /aem-dam/Solutions/events/ces-2022/news/geforce-rtx-3050-graphics-cards/nvidia-c", "u": "https://images.nvidia.com/aem-dam/Solutions/events/ces-2022/news/geforce-rtx-3050-graphics-cards/nvidia-ces-2022-rtx-3050-c-large-3840.png" }, { "t": "pny.com — /pny-geforce-rtx-3050-8gb-verto-dual-fan", "u": "https://www.pny.com/pny-geforce-rtx-3050-8gb-verto-dual-fan" }, { "t": "nvidia.com — /en-us/geforce/graphics-cards/compare/", "u": "https://www.nvidia.com/en-us/geforce/graphics-cards/compare/" }, { "t": "en.wikipedia.org — /wiki/GeForce_30_series", "u": "https://en.wikipedia.org/wiki/GeForce_30_series" } ], "aka": null }, { "id": "rtx-3080-12gb", "name": "GeForce RTX 3080 12GB", "short": "RTX 3080 12GB", "seg": "geforce", "arch": "Ampere", "archGroup": "Ampere", "cls": "ampere-geforce", "clsLabel": "Ampere GA10x (GF)", "chip": "GA102", "date": "2022-01", "t": 2022.0, "status": null, "ff": "desktop PCIe card", "mem": 12.0, "memType": "GDDR6X", "bw": 912.0, "tdp": 350.0, "sms": 70.0, "tc": 280.0, "cuda": 8960.0, "boost": 1710.0, "v": { "fp32": [ 30.6432, null, "d" ], "fp64": [ 0.4788, null, "d" ], "tf32": [ 30.6432, 61.2864, "d" ], "fp16": [ 61.2864, 122.5728, "d" ], "bf16": [ 61.2864, 122.5728, "d" ], "int8": [ 245.1456, 490.2912, "d" ], "int4": [ 490.2912, 980.5824, "d" ], "fp16a16": [ 122.5728, 245.1456, "d" ] }, "how": { "fp32": "Derived: 2 × 8,960 CUDA cores × 1,710 MHz boost clock", "fp64": "Derived: FP32 ÷ 64 (this architecture's FP64 rate)", "tf32": "Derived: 70 SMs × 1,710 MHz boost clock × 256 TF32 ops per clock per SM on GeForce Ampere. NVIDIA publishes no tensor figure for this card", "fp16": "Derived: 70 SMs × 1,710 MHz boost clock × 512 FP16 (FP32 accumulate) ops per clock per SM on GeForce Ampere. NVIDIA publishes no tensor figure for this card", "bf16": "Derived: 70 SMs × 1,710 MHz boost clock × 512 BF16 ops per clock per SM on GeForce Ampere. NVIDIA publishes no tensor figure for this card", "int8": "Derived: 70 SMs × 1,710 MHz boost clock × 2,048 INT8 ops per clock per SM on GeForce Ampere. NVIDIA publishes no tensor figure for this card", "int4": "Derived: 70 SMs × 1,710 MHz boost clock × 4,096 INT4 ops per clock per SM on GeForce Ampere. NVIDIA publishes no tensor figure for this card", "fp16a16": "Derived: 70 SMs × 1,710 MHz boost clock × 1,024 FP16 (FP16 accumulate) ops per clock per SM on GeForce Ampere. NVIDIA publishes no tensor figure for this card" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "fp8": "No FP8 tensor cores before Ada/Hopper (FP8 models run at FP16 speed)", "fp6": "No FP6 tensor cores before Blackwell", "fp4": "No FP4 tensor cores before Blackwell" }, "headline": null, "anchor": "Derived from 70 SMs × 1,710 MHz boost clock. ", "notes": "NVIDIA published no throughput figure and made no press release. The card shares the RTX 3080 column on NVIDIA's spec page; the single 1.71 GHz boost applies to both 10GB and 12GB. No Founders Edition.", "sources": [ { "t": "nvidia.com — /en-us/geforce/graphics-cards/30-series/rtx-3080-3080ti/", "u": "https://www.nvidia.com/en-us/geforce/graphics-cards/30-series/rtx-3080-3080ti/" }, { "t": "pny.com — /geforce-rtx-3080-12gb-uprising-tf-lhr", "u": "https://www.pny.com/geforce-rtx-3080-12gb-uprising-tf-lhr" }, { "t": "guru3d.com — /story/nvidia-geforce-rtx-3080-12gb-is-now-official/", "u": "https://www.guru3d.com/story/nvidia-geforce-rtx-3080-12gb-is-now-official/" }, { "t": "en.wikipedia.org — /wiki/GeForce_30_series", "u": "https://en.wikipedia.org/wiki/GeForce_30_series" } ], "aka": null }, { "id": "rtx-2060-12gb", "name": "GeForce RTX 2060 12GB", "short": "RTX 2060 12GB", "seg": "geforce", "arch": "Turing", "archGroup": "Turing", "cls": "turing-geforce", "clsLabel": "Turing (GF)", "chip": "TU106", "date": "2021-12", "t": 2021.9166666666667, "status": null, "ff": "desktop PCIe card", "mem": 12.0, "memType": "GDDR6", "bw": null, "tdp": 185.0, "sms": 34.0, "tc": 272.0, "cuda": 2176.0, "boost": 1650.0, "v": { "fp32": [ 7.1808, null, "d" ], "fp64": [ 0.2244, null, "d" ], "fp16": [ 28.7232, null, "d" ], "int8": [ 114.8928, null, "d" ], "int4": [ 229.7856, null, "d" ], "fp16a16": [ 57.4464, null, "d" ] }, "how": { "fp32": "Derived: 2 × 2,176 CUDA cores × 1,650 MHz boost clock", "fp64": "Derived: FP32 ÷ 32 (this architecture's FP64 rate)", "fp16": "Derived: 34 SMs × 1,650 MHz boost clock × 512 FP16 (FP32 accumulate) ops per clock per SM on GeForce Turing. NVIDIA publishes no tensor figure for this card", "int8": "Derived: 34 SMs × 1,650 MHz boost clock × 2,048 INT8 ops per clock per SM on GeForce Turing. NVIDIA publishes no tensor figure for this card", "int4": "Derived: 34 SMs × 1,650 MHz boost clock × 4,096 INT4 ops per clock per SM on GeForce Turing. NVIDIA publishes no tensor figure for this card", "fp16a16": "Derived: 34 SMs × 1,650 MHz boost clock × 1,024 FP16 (FP16 accumulate) ops per clock per SM on GeForce Turing. NVIDIA publishes no tensor figure for this card" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "tf32": "TF32 tensor cores arrived with Ampere", "bf16": "BF16 tensor cores arrived with Ampere", "fp8": "No FP8 tensor cores before Ada/Hopper (FP8 models run at FP16 speed)", "fp6": "No FP6 tensor cores before Blackwell", "fp4": "No FP4 tensor cores before Blackwell" }, "headline": null, "anchor": "Derived from 34 SMs × 1,650 MHz boost clock. ", "notes": "NVIDIA published no throughput figure for this card. There was no press release or dedicated page; specs appear only on the compare page, shared with the 6GB column. The rtx-2060 page redirected to /geforce/20-series/ from Dec 2021, so no archived 12GB spec page exists. Bandwidth left null: neither NVIDIA nor the ASUS page prints it. Guru3D (Dec 2, 2021) and Wikipedia list 336 GB/s. No Founders Edition.", "sources": [ { "t": "nvidia.com — /en-us/geforce/graphics-cards/compare/", "u": "https://www.nvidia.com/en-us/geforce/graphics-cards/compare/" }, { "t": "asus.com — /motherboards-components/graphics-cards/dual/dual-rtx2060-12g-evo/techspec/", "u": "https://www.asus.com/motherboards-components/graphics-cards/dual/dual-rtx2060-12g-evo/techspec/" }, { "t": "guru3d.com — /story/nvidia-reveals-geforce-rtx-2060-12gb-final-gpu-specifications", "u": "https://www.guru3d.com/story/nvidia-reveals-geforce-rtx-2060-12gb-final-gpu-specifications" }, { "t": "en.wikipedia.org — /wiki/GeForce_20_series", "u": "https://en.wikipedia.org/wiki/GeForce_20_series" } ], "aka": null }, { "id": "rtx-3070-ti", "name": "GeForce RTX 3070 Ti", "short": "RTX 3070 Ti", "seg": "geforce", "arch": "Ampere", "archGroup": "Ampere", "cls": "ampere-geforce", "clsLabel": "Ampere GA10x (GF)", "chip": "GA104", "date": "2021-06", "t": 2021.4166666666667, "status": null, "ff": "desktop PCIe card", "mem": 8.0, "memType": "GDDR6X", "bw": 608.0, "tdp": 290.0, "sms": 48.0, "tc": 192.0, "cuda": 6144.0, "boost": 1770.0, "v": { "fp32": [ 22.0, null, "p" ], "fp64": [ 0.3438, null, "d" ], "tf32": [ 21.75, 43.5, "d" ], "fp16": [ 43.5, 87.0, "d" ], "bf16": [ 43.5, 87.0, "d" ], "int8": [ 174.0, 348.0, "d" ], "int4": [ 348.0, 696.0, "d" ], "fp16a16": [ 87.0, 174.0, "p" ] }, "how": { "fp32": "NVIDIA: “GEFORCE RTX 3070 Ti: 22 Shader-TFLOPS | 42 RT-TFLOPS | 174 Tensor-TFLOPS” [nvidia.com]", "fp64": "Derived: FP32 ÷ 64 (this architecture's FP64 rate)", "tf32": "Derived from NVIDIA's headline figure, 174 TFLOPS FP16 with sparsity (so 87 dense). On GeForce Ampere, TF32 runs at a quarter of the FP16 (FP16 accumulate) rate", "fp16": "Derived from NVIDIA's headline figure, 174 TFLOPS FP16 with sparsity (so 87 dense). On GeForce Ampere, FP16 (FP32 accumulate) runs at half the FP16 (FP16 accumulate) rate", "bf16": "Derived from NVIDIA's headline figure, 174 TFLOPS FP16 with sparsity (so 87 dense). On GeForce Ampere, BF16 runs at half the FP16 (FP16 accumulate) rate", "int8": "Derived from NVIDIA's headline figure, 174 TFLOPS FP16 with sparsity (so 87 dense). On GeForce Ampere, INT8 runs at twice the FP16 (FP16 accumulate) rate", "int4": "Derived from NVIDIA's headline figure, 174 TFLOPS FP16 with sparsity (so 87 dense). On GeForce Ampere, INT4 runs at 4× the FP16 (FP16 accumulate) rate", "fp16a16": "NVIDIA: “174 Tensor-TFLOPS” (precision not stated; GeForce Ampere headline figures are FP16) (sparsity not stated; NVIDIA's headline figures include it from Ampere on, and the card's clock confirms it) (dense = half the sparse figure) [nvidia.com]" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "fp8": "No FP8 tensor cores before Ada/Hopper (FP8 models run at FP16 speed)", "fp6": "No FP6 tensor cores before Blackwell", "fp4": "No FP4 tensor cores before Blackwell" }, "headline": "“174 Tensor-TFLOPS”", "anchor": "Derived from NVIDIA's headline figure, 174 TFLOPS FP16 with sparsity (so 87 dense). ", "notes": "Throughput figures appear only in the Computex 2021 slide image embedded in NVIDIA's GeForce news article 'It's Time For Ti'. The article text and press release give none. Per Wikipedia, a GA102-150 variant appeared in Oct 2022. Founders Edition exists at reference clocks.", "sources": [ { "t": "nvidia.com — /en-us/geforce/graphics-cards/30-series/rtx-3070-3070ti/", "u": "https://www.nvidia.com/en-us/geforce/graphics-cards/30-series/rtx-3070-3070ti/" }, { "t": "nvidia.com — /en-us/geforce/news/rtx-3080-ti-3070-ti-graphics-cards/", "u": "https://www.nvidia.com/en-us/geforce/news/rtx-3080-ti-3070-ti-graphics-cards/" }, { "t": "nvidia.com — /content/dam/en-zz/Solutions/geforce/news/rtx-3080-ti-3070-ti-graphics-cards/nvi", "u": "https://www.nvidia.com/content/dam/en-zz/Solutions/geforce/news/rtx-3080-ti-3070-ti-graphics-cards/nvidia-geforce-computex-2021-introducing-rtx-3070-ti.jpg" }, { "t": "nvidianews.nvidia.com — /news/its-time-for-ti-nvidia-introduces-gaming-flagship-the-geforce-rtx-3080-ti", "u": "https://nvidianews.nvidia.com/news/its-time-for-ti-nvidia-introduces-gaming-flagship-the-geforce-rtx-3080-ti" }, { "t": "pny.com — /pny-geforce-rtx-3070-ti-8gb-verto-triple-fan", "u": "https://www.pny.com/pny-geforce-rtx-3070-ti-8gb-verto-triple-fan" }, { "t": "en.wikipedia.org — /wiki/GeForce_30_series", "u": "https://en.wikipedia.org/wiki/GeForce_30_series" } ], "aka": null }, { "id": "rtx-3080-ti", "name": "GeForce RTX 3080 Ti", "short": "RTX 3080 Ti", "seg": "geforce", "arch": "Ampere", "archGroup": "Ampere", "cls": "ampere-geforce", "clsLabel": "Ampere GA10x (GF)", "chip": "GA102", "date": "2021-06", "t": 2021.4166666666667, "status": null, "ff": "desktop PCIe card", "mem": 12.0, "memType": "GDDR6X", "bw": 912.0, "tdp": 350.0, "sms": 80.0, "tc": 320.0, "cuda": 10240.0, "boost": 1665.0, "v": { "fp32": [ 34.1, null, "p" ], "fp64": [ 0.5328, null, "d" ], "tf32": [ 34.1, 68.2, "p" ], "fp16": [ 68.2, 136.4, "p" ], "bf16": [ 68.2, 136.4, "p" ], "int8": [ 272.8, 545.6, "p" ], "int4": [ 545.6, 1091.2, "p" ], "fp16a16": [ 136.4, 272.8, "p" ] }, "how": { "fp32": "NVIDIA: “Table 3: Peak FP32 TFLOPS (non-Tensor) 34.1” [images.nvidia.com]", "fp64": "Derived: FP32 ÷ 64 (this architecture's FP64 rate)", "tf32": "NVIDIA: “Table 3: Peak TF32 Tensor TFLOPS 34.1/68.2” [images.nvidia.com]", "fp16": "NVIDIA: “Table 3: Peak FP16 Tensor TFLOPS with FP32 Accumulate 68.2/136.4” [images.nvidia.com]", "bf16": "NVIDIA: “Table 3: Peak BF16 Tensor TFLOPS with FP32 Accumulate 68.2/136.4” [images.nvidia.com]", "int8": "NVIDIA: “Table 3: Peak INT8 Tensor TOPS 272.8/545.6” [images.nvidia.com]", "int4": "NVIDIA: “Table 3: Peak INT4 Tensor TOPS 545.6/1091.2” [images.nvidia.com]", "fp16a16": "NVIDIA: “Table 3: Peak FP16 Tensor TFLOPS with FP16 Accumulate 136.4/272.8” [images.nvidia.com]" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "fp8": "No FP8 tensor cores before Ada/Hopper (FP8 models run at FP16 speed)", "fp6": "No FP6 tensor cores before Blackwell", "fp4": "No FP4 tensor cores before Blackwell" }, "headline": "“The GeForce RTX 3080 Ti’s power comes from 34 Shader-TeraFLOPS, 67 RT-TeraFLOPS, 273 Tensor-TeraFLOPS”", "anchor": "Derived from NVIDIA's published FP16 (FP16 accumulate) figure of 136.4 dense. ", "notes": "Per-precision table from the Ada whitepaper v2.02 Appendix B, Table 3 'GeForce RTX 4080 16 GB vs 3080 Ti vs 2080 Super'. The GA102 whitepaper predates this card. The Computex slide image repeats '34 Shader-TFLOPS | 67 RT-TFLOPS | 273 Tensor-TFLOPS'. The spec page rounds the boost to 1.67 GHz. Founders Edition at reference clocks. GeForce half-rate pattern visible.", "sources": [ { "t": "images.nvidia.com — /aem-dam/Solutions/geforce/ada/nvidia-ada-gpu-architecture.pdf", "u": "https://images.nvidia.com/aem-dam/Solutions/geforce/ada/nvidia-ada-gpu-architecture.pdf" }, { "t": "nvidia.com — /en-us/geforce/graphics-cards/30-series/rtx-3080-3080ti/", "u": "https://www.nvidia.com/en-us/geforce/graphics-cards/30-series/rtx-3080-3080ti/" }, { "t": "nvidia.com — /en-us/geforce/news/computex-2021-announcements/", "u": "https://www.nvidia.com/en-us/geforce/news/computex-2021-announcements/" }, { "t": "nvidia.com — /content/dam/en-zz/Solutions/geforce/news/rtx-3080-ti-3070-ti-graphics-cards/nvi", "u": "https://www.nvidia.com/content/dam/en-zz/Solutions/geforce/news/rtx-3080-ti-3070-ti-graphics-cards/nvidia-geforce-computex-2021-introducing-rtx-3080-ti.jpg" }, { "t": "nvidianews.nvidia.com — /news/its-time-for-ti-nvidia-introduces-gaming-flagship-the-geforce-rtx-3080-ti", "u": "https://nvidianews.nvidia.com/news/its-time-for-ti-nvidia-introduces-gaming-flagship-the-geforce-rtx-3080-ti" } ], "aka": null }, { "id": "rtx-3060-12gb", "name": "GeForce RTX 3060 12GB", "short": "RTX 3060 12GB", "seg": "geforce", "arch": "Ampere", "archGroup": "Ampere", "cls": "ampere-geforce", "clsLabel": "Ampere GA10x (GF)", "chip": "GA106", "date": "2021-02", "t": 2021.0833333333333, "status": null, "ff": "desktop PCIe card", "mem": 12.0, "memType": "GDDR6", "bw": 360.0, "tdp": 170.0, "sms": 28.0, "tc": 112.0, "cuda": 3584.0, "boost": 1780.0, "v": { "fp32": [ 13.0, null, "p" ], "fp64": [ 0.2031, null, "d" ], "tf32": [ 12.625, 25.25, "d" ], "fp16": [ 25.25, 50.5, "d" ], "bf16": [ 25.25, 50.5, "d" ], "int8": [ 101.0, 202.0, "d" ], "int4": [ 202.0, 404.0, "d" ], "fp16a16": [ 50.5, 101.0, "p" ] }, "how": { "fp32": "NVIDIA: “The RTX 3060’s key specifications include: 13 shader-TFLOPs” [nvidianews.nvidia.com]", "fp64": "Derived: FP32 ÷ 64 (this architecture's FP64 rate)", "tf32": "Derived from NVIDIA's headline figure, 101 TFLOPS FP16 with sparsity (so 50.5 dense). On GeForce Ampere, TF32 runs at a quarter of the FP16 (FP16 accumulate) rate", "fp16": "Derived from NVIDIA's headline figure, 101 TFLOPS FP16 with sparsity (so 50.5 dense). On GeForce Ampere, FP16 (FP32 accumulate) runs at half the FP16 (FP16 accumulate) rate", "bf16": "Derived from NVIDIA's headline figure, 101 TFLOPS FP16 with sparsity (so 50.5 dense). On GeForce Ampere, BF16 runs at half the FP16 (FP16 accumulate) rate", "int8": "Derived from NVIDIA's headline figure, 101 TFLOPS FP16 with sparsity (so 50.5 dense). On GeForce Ampere, INT8 runs at twice the FP16 (FP16 accumulate) rate", "int4": "Derived from NVIDIA's headline figure, 101 TFLOPS FP16 with sparsity (so 50.5 dense). On GeForce Ampere, INT4 runs at 4× the FP16 (FP16 accumulate) rate", "fp16a16": "NVIDIA: “101 tensor-TFLOPs to power NVIDIA DLSS (Deep Learning Super Sampling)” (precision not stated; GeForce Ampere headline figures are FP16) (sparsity not stated; NVIDIA's headline figures include it from Ampere on, and the card's clock confirms it) (dense = half the sparse figure) [nvidianews.nvidia.com]" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "fp8": "No FP8 tensor cores before Ada/Hopper (FP8 models run at FP16 speed)", "fp6": "No FP6 tensor cores before Blackwell", "fp4": "No FP4 tensor cores before Blackwell" }, "headline": "“101 tensor-TFLOPs to power NVIDIA DLSS (Deep Learning Super Sampling)”", "anchor": "Derived from NVIDIA's headline figure, 101 TFLOPS FP16 with sparsity (so 50.5 dense). ", "notes": "Press release (Jan 12, 2021) also gives '25 RT-TFLOPs for ray tracing'. Reference-clocked PNY board boost: 1777 MHz. Per Wikipedia, LHR (GA106-302) and GA104-150 variants followed in 2021. No Founders Edition.", "sources": [ { "t": "nvidianews.nvidia.com — /news/nvidia-introduces-geforce-rtx-3060-next-generation-of-the-worlds-most-popu", "u": "https://nvidianews.nvidia.com/news/nvidia-introduces-geforce-rtx-3060-next-generation-of-the-worlds-most-popular-gpu" }, { "t": "nvidia.com — /en-us/geforce/graphics-cards/30-series/rtx-3060-3060ti/", "u": "https://www.nvidia.com/en-us/geforce/graphics-cards/30-series/rtx-3060-3060ti/" }, { "t": "pny.com — /pny-geforce-rtx3060-12gb-verto-dual-fan", "u": "https://www.pny.com/pny-geforce-rtx3060-12gb-verto-dual-fan" }, { "t": "nvidia.com — /en-us/geforce/graphics-cards/compare/", "u": "https://www.nvidia.com/en-us/geforce/graphics-cards/compare/" }, { "t": "en.wikipedia.org — /wiki/GeForce_30_series", "u": "https://en.wikipedia.org/wiki/GeForce_30_series" } ], "aka": null }, { "id": "rtx-3060-ti", "name": "GeForce RTX 3060 Ti", "short": "RTX 3060 Ti", "seg": "geforce", "arch": "Ampere", "archGroup": "Ampere", "cls": "ampere-geforce", "clsLabel": "Ampere GA10x (GF)", "chip": "GA104", "date": "2020-12", "t": 2020.9166666666667, "status": null, "ff": "desktop PCIe card", "mem": 8.0, "memType": "GDDR6", "bw": 448.0, "tdp": 200.0, "sms": 38.0, "tc": 152.0, "cuda": 4864.0, "boost": 1670.0, "v": { "fp32": [ 16.2458, null, "d" ], "fp64": [ 0.2538, null, "d" ], "tf32": [ 16.2458, 32.4915, "d" ], "fp16": [ 32.4915, 64.983, "d" ], "bf16": [ 32.4915, 64.983, "d" ], "int8": [ 129.9661, 259.9322, "d" ], "int4": [ 259.9322, 519.8643, "d" ], "fp16a16": [ 64.983, 129.9661, "d" ] }, "how": { "fp32": "Derived: 2 × 4,864 CUDA cores × 1,670 MHz boost clock", "fp64": "Derived: FP32 ÷ 64 (this architecture's FP64 rate)", "tf32": "Derived: 38 SMs × 1,670 MHz boost clock × 256 TF32 ops per clock per SM on GeForce Ampere. NVIDIA publishes no tensor figure for this card", "fp16": "Derived: 38 SMs × 1,670 MHz boost clock × 512 FP16 (FP32 accumulate) ops per clock per SM on GeForce Ampere. NVIDIA publishes no tensor figure for this card", "bf16": "Derived: 38 SMs × 1,670 MHz boost clock × 512 BF16 ops per clock per SM on GeForce Ampere. NVIDIA publishes no tensor figure for this card", "int8": "Derived: 38 SMs × 1,670 MHz boost clock × 2,048 INT8 ops per clock per SM on GeForce Ampere. NVIDIA publishes no tensor figure for this card", "int4": "Derived: 38 SMs × 1,670 MHz boost clock × 4,096 INT4 ops per clock per SM on GeForce Ampere. NVIDIA publishes no tensor figure for this card", "fp16a16": "Derived: 38 SMs × 1,670 MHz boost clock × 1,024 FP16 (FP16 accumulate) ops per clock per SM on GeForce Ampere. NVIDIA publishes no tensor figure for this card" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "fp8": "No FP8 tensor cores before Ada/Hopper (FP8 models run at FP16 speed)", "fp6": "No FP6 tensor cores before Blackwell", "fp4": "No FP4 tensor cores before Blackwell" }, "headline": null, "anchor": "Derived from 38 SMs × 1,670 MHz boost clock. ", "notes": "No NVIDIA-hosted throughput figure was found. The press release, the GeForce news article, and the Jan 2021 archived spec page have none. Press reviews quote '16 Shader / 32 RT / 130 Tensor TFLOPS', apparently from reviewer materials; not recorded. The NVIDIA page also lists an 8 GB GDDR6X variant (2022). PNY's non-LHR 'VERTO Dual Fan' URL now shows that variant (19 Gbps, 608 GB/s, 225 W), so the LHR GDDR6 page was used. Founders Edition exists and runs at reference clocks.", "sources": [ { "t": "nvidia.com — /en-us/geforce/graphics-cards/30-series/rtx-3060-3060ti/", "u": "https://www.nvidia.com/en-us/geforce/graphics-cards/30-series/rtx-3060-3060ti/" }, { "t": "nvidianews.nvidia.com — /news/nvidia-debuts-geforce-rtx-3060-family-for-the-holidays", "u": "https://nvidianews.nvidia.com/news/nvidia-debuts-geforce-rtx-3060-family-for-the-holidays" }, { "t": "nvidia.com — /en-us/geforce/news/geforce-rtx-3060-ti-out-december-2/", "u": "https://www.nvidia.com/en-us/geforce/news/geforce-rtx-3060-ti-out-december-2/" }, { "t": "pny.com — /pny-geforce-rtx-3060-ti-8gb-verto-dual-fan-lhr", "u": "https://www.pny.com/pny-geforce-rtx-3060-ti-8gb-verto-dual-fan-lhr" }, { "t": "en.wikipedia.org — /wiki/GeForce_30_series", "u": "https://en.wikipedia.org/wiki/GeForce_30_series" } ], "aka": null }, { "id": "rtx-3070", "name": "GeForce RTX 3070", "short": "RTX 3070", "seg": "geforce", "arch": "Ampere", "archGroup": "Ampere", "cls": "ampere-geforce", "clsLabel": "Ampere GA10x (GF)", "chip": "GA104", "date": "2020-10", "t": 2020.75, "status": null, "ff": "desktop PCIe card", "mem": 8.0, "memType": "GDDR6", "bw": 448.0, "tdp": 220.0, "sms": 46.0, "tc": 184.0, "cuda": 5888.0, "boost": 1725.0, "v": { "fp32": [ 20.3, null, "p" ], "fp64": [ 0.3172, null, "d" ], "tf32": [ 20.3, 40.6, "p" ], "fp16": [ 40.6, 81.3, "p" ], "bf16": [ 40.6, 81.3, "p" ], "int8": [ 162.6, 325.2, "p" ], "int4": [ 325.2, 650.4, "p" ], "fp16a16": [ 81.3, 162.6, "p" ] }, "how": { "fp32": "NVIDIA: “Table 10: Peak FP32 TFLOPS (non-Tensor) 20.3” [nvidia.com]", "fp64": "Derived: FP32 ÷ 64 (this architecture's FP64 rate)", "tf32": "NVIDIA: “Table 10: Peak TF32 Tensor TFLOPS 20.3/40.6” [nvidia.com]", "fp16": "NVIDIA: “Table 10: Peak FP16 Tensor TFLOPS with FP32 Accumulate 40.6/81.3” [nvidia.com]", "bf16": "NVIDIA: “Table 10: Peak BF16 Tensor TFLOPS with FP32 Accumulate 40.6/81.3” [nvidia.com]", "int8": "NVIDIA: “Table 10: Peak INT8 Tensor TOPS 162.6/325.2” [nvidia.com]", "int4": "NVIDIA: “Table 10: Peak INT4 Tensor TOPS 325.2/650.4” [nvidia.com]", "fp16a16": "NVIDIA: “Table 10: Peak FP16 Tensor TFLOPS with FP16 Accumulate 81.3/162.6” [nvidia.com]" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "fp8": "No FP8 tensor cores before Ada/Hopper (FP8 models run at FP16 speed)", "fp6": "No FP6 tensor cores before Blackwell", "fp4": "No FP4 tensor cores before Blackwell" }, "headline": null, "anchor": "Derived from NVIDIA's published FP16 (FP16 accumulate) figure of 81.3 dense. ", "notes": "Whitepaper column 'RTX 3070 Founders Edition'. The spec page rounds the boost to 1.73 GHz; values are at 1725 MHz. GeForce half-rate pattern: FP16-acc32 = BF16 = half of FP16-acc16, and TF32 = half of BF16. Table 10 footnotes are misnumbered 4-6. The keynote headline '163 Tensor-TFLOPS' widely quoted in press was not found on any NVIDIA-hosted page, so it is not recorded.", "sources": [ { "t": "nvidia.com — /content/PDF/nvidia-ampere-ga-102-gpu-architecture-whitepaper-v2.1.pdf", "u": "https://www.nvidia.com/content/PDF/nvidia-ampere-ga-102-gpu-architecture-whitepaper-v2.1.pdf" }, { "t": "nvidia.com — /content/PDF/nvidia-ampere-ga-102-gpu-architecture-whitepaper-v2.pdf", "u": "https://www.nvidia.com/content/PDF/nvidia-ampere-ga-102-gpu-architecture-whitepaper-v2.pdf" }, { "t": "nvidia.com — /en-us/geforce/graphics-cards/30-series/rtx-3070-3070ti/", "u": "https://www.nvidia.com/en-us/geforce/graphics-cards/30-series/rtx-3070-3070ti/" }, { "t": "nvidia.com — /en-us/geforce/news/geforce-rtx-3070-out-now/", "u": "https://www.nvidia.com/en-us/geforce/news/geforce-rtx-3070-out-now/" }, { "t": "nvidianews.nvidia.com — /news/nvidia-delivers-greatest-ever-generational-leap-in-performance-with-geforc", "u": "https://nvidianews.nvidia.com/news/nvidia-delivers-greatest-ever-generational-leap-in-performance-with-geforce-rtx-30-series-gpus" } ], "aka": null }, { "id": "rtx-3080-10gb", "name": "GeForce RTX 3080 10GB", "short": "RTX 3080 10GB", "seg": "geforce", "arch": "Ampere", "archGroup": "Ampere", "cls": "ampere-geforce", "clsLabel": "Ampere GA10x (GF)", "chip": "GA102", "date": "2020-09", "t": 2020.6666666666667, "status": null, "ff": "desktop PCIe card", "mem": 10.0, "memType": "GDDR6X", "bw": 760.0, "tdp": 320.0, "sms": 68.0, "tc": 272.0, "cuda": 8704.0, "boost": 1710.0, "v": { "fp32": [ 29.8, null, "p" ], "fp64": [ 0.4656, null, "d" ], "tf32": [ 29.8, 59.5, "p" ], "fp16": [ 59.5, 119.0, "p" ], "bf16": [ 59.5, 119.0, "p" ], "int8": [ 238.0, 476.0, "p" ], "int4": [ 476.0, 952.0, "p" ], "fp16a16": [ 119.0, 238.0, "p" ] }, "how": { "fp32": "NVIDIA: “Table 2: Peak FP32 TFLOPS (non-Tensor) 29.8” [nvidia.com]", "fp64": "Derived: FP32 ÷ 64 (this architecture's FP64 rate)", "tf32": "NVIDIA: “Table 2: Peak TF32 Tensor TFLOPS 29.8/59.5” [nvidia.com]", "fp16": "NVIDIA: “Table 2: Peak FP16 Tensor TFLOPS with FP32 Accumulate 59.5/119” [nvidia.com]", "bf16": "NVIDIA: “Table 2: Peak BF16 Tensor TFLOPS with FP32 Accumulate 59.5/119” [nvidia.com]", "int8": "NVIDIA: “Table 2: Peak INT8 Tensor TOPS 238/476” [nvidia.com]", "int4": "NVIDIA: “Table 2: Peak INT4 Tensor TOPS 476/952” [nvidia.com]", "fp16a16": "NVIDIA: “Table 2: Peak FP16 Tensor TFLOPS with FP16 Accumulate 119/238” [nvidia.com]" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "fp8": "No FP8 tensor cores before Ada/Hopper (FP8 models run at FP16 speed)", "fp6": "No FP6 tensor cores before Blackwell", "fp4": "No FP4 tensor cores before Blackwell" }, "headline": null, "anchor": "Derived from NVIDIA's published FP16 (FP16 accumulate) figure of 119 dense. ", "notes": "WP text (p.25) confirms: 'the GeForce RTX 3080 GPU delivers 119 peak FP16 Tensor TFLOPS with FP16 accumulate, and with Sparsity enabled, 238 ... RTX 3080 delivers 238 peak INT8 Tensor TOPS and 476 peak INT4 Tensor TOPS, and double those rates with Sparsity enabled.' The launch press release and the 'NEW AMPERE ARCHITECTURE' image (https://www.nvidia.com/content/dam/en-zz/Solutions/geforce/news/geforce-rtx-30-series/geforce-rtx-30-series-2nd-gen-ampere-architecture.jpg) give '30 Shader-TFLOPS | 58 RT-TFLOPS | 238 Tensor-TFLOPS' without naming the card. They match the 3080's FP32 29.8 and sparse FP16-acc16 238, so they are not recorded as a separate headline. GeForce half-rate pattern visible.", "sources": [ { "t": "nvidia.com — /content/PDF/nvidia-ampere-ga-102-gpu-architecture-whitepaper-v2.1.pdf", "u": "https://www.nvidia.com/content/PDF/nvidia-ampere-ga-102-gpu-architecture-whitepaper-v2.1.pdf" }, { "t": "nvidia.com — /content/PDF/nvidia-ampere-ga-102-gpu-architecture-whitepaper-v2.pdf", "u": "https://www.nvidia.com/content/PDF/nvidia-ampere-ga-102-gpu-architecture-whitepaper-v2.pdf" }, { "t": "nvidia.com — /en-us/geforce/graphics-cards/30-series/rtx-3080-3080ti/", "u": "https://www.nvidia.com/en-us/geforce/graphics-cards/30-series/rtx-3080-3080ti/" }, { "t": "nvidianews.nvidia.com — /news/nvidia-delivers-greatest-ever-generational-leap-in-performance-with-geforc", "u": "https://nvidianews.nvidia.com/news/nvidia-delivers-greatest-ever-generational-leap-in-performance-with-geforce-rtx-30-series-gpus" }, { "t": "nvidia.com — /en-us/geforce/news/introducing-rtx-30-series-graphics-cards/", "u": "https://www.nvidia.com/en-us/geforce/news/introducing-rtx-30-series-graphics-cards/" } ], "aka": null }, { "id": "rtx-3090", "name": "GeForce RTX 3090", "short": "RTX 3090", "seg": "geforce", "arch": "Ampere", "archGroup": "Ampere", "cls": "ampere-geforce", "clsLabel": "Ampere GA10x (GF)", "chip": "GA102", "date": "2020-09", "t": 2020.6666666666667, "status": null, "ff": "3-slot desktop PCIe card (Founders Edition)", "mem": 24.0, "memType": "GDDR6X", "bw": 936.0, "tdp": 350.0, "sms": 82.0, "tc": 328.0, "cuda": 10496.0, "boost": 1695.0, "v": { "fp32": [ 35.6, null, "p" ], "fp64": [ 0.5563, null, "d" ], "tf32": [ 35.6, 71.0, "p" ], "fp16": [ 71.0, 142.0, "p" ], "bf16": [ 71.0, 142.0, "p" ], "int8": [ 284.0, 568.0, "p" ], "int4": [ 568.0, 1136.0, "p" ], "fp16a16": [ 142.0, 284.0, "p" ] }, "how": { "fp32": "NVIDIA: “Table 9: Peak FP32 TFLOPS (non-Tensor) 35.6” [nvidia.com]", "fp64": "Derived: FP32 ÷ 64 (this architecture's FP64 rate)", "tf32": "NVIDIA: “Table 9: Peak TF32 Tensor TFLOPS 35.6/71” [nvidia.com]", "fp16": "NVIDIA: “Table 9: Peak FP16 Tensor TFLOPS with FP32 Accumulate 71/142” [nvidia.com]", "bf16": "NVIDIA: “Table 9: Peak BF16 Tensor TFLOPS with FP32 Accumulate 71/142” [nvidia.com]", "int8": "NVIDIA: “Table 9: Peak INT8 Tensor TOPS 284/568” [nvidia.com]", "int4": "NVIDIA: “Table 9: Peak INT4 Tensor TOPS 568/1136” [nvidia.com]", "fp16a16": "NVIDIA: “Table 9: Peak FP16 Tensor TFLOPS with FP16 Accumulate 142/284” [nvidia.com]" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "fp8": "No FP8 tensor cores before Ada/Hopper (FP8 models run at FP16 speed)", "fp6": "No FP6 tensor cores before Blackwell", "fp4": "No FP4 tensor cores before Blackwell" }, "headline": null, "anchor": "Derived from NVIDIA's published FP16 (FP16 accumulate) figure of 142 dense. ", "notes": "Whitepaper column 'RTX 3090 FE Founders Edition'. The spec page rounds the boost to 1.70 GHz; values are at 1695 MHz. KEY contrast in the same whitepaper: the RTX A6000 (same GA102 die, 84 SMs) is full rate with FP32 accumulate (154.8 for FP16-acc16, FP16-acc32 and BF16; TF32 77.4). The RTX 3090 is half rate (142 vs 71; TF32 35.6). The keynote headline '285 Tensor-TFLOPS' quoted in press was not found on any NVIDIA-hosted page, so it is not recorded.", "sources": [ { "t": "nvidia.com — /content/PDF/nvidia-ampere-ga-102-gpu-architecture-whitepaper-v2.1.pdf", "u": "https://www.nvidia.com/content/PDF/nvidia-ampere-ga-102-gpu-architecture-whitepaper-v2.1.pdf" }, { "t": "nvidia.com — /content/PDF/nvidia-ampere-ga-102-gpu-architecture-whitepaper-v2.pdf", "u": "https://www.nvidia.com/content/PDF/nvidia-ampere-ga-102-gpu-architecture-whitepaper-v2.pdf" }, { "t": "nvidia.com — /en-us/geforce/graphics-cards/30-series/rtx-3090-3090ti/", "u": "https://www.nvidia.com/en-us/geforce/graphics-cards/30-series/rtx-3090-3090ti/" }, { "t": "nvidianews.nvidia.com — /news/nvidia-delivers-greatest-ever-generational-leap-in-performance-with-geforc", "u": "https://nvidianews.nvidia.com/news/nvidia-delivers-greatest-ever-generational-leap-in-performance-with-geforce-rtx-30-series-gpus" } ], "aka": null }, { "id": "rtx-2060-super", "name": "GeForce RTX 2060 SUPER", "short": "RTX 2060 SUPER", "seg": "geforce", "arch": "Turing", "archGroup": "Turing", "cls": "turing-geforce", "clsLabel": "Turing (GF)", "chip": "TU106", "date": "2019-07", "t": 2019.5, "status": null, "ff": "desktop PCIe card", "mem": 8.0, "memType": "GDDR6", "bw": 448.0, "tdp": 175.0, "sms": 34.0, "tc": 272.0, "cuda": 2176.0, "boost": 1650.0, "v": { "fp32": [ 7.0, null, "p" ], "fp64": [ 0.2188, null, "d" ], "fp16": [ 28.5, null, "d" ], "int8": [ 114.0, null, "d" ], "int4": [ 228.0, null, "d" ], "fp16a16": [ 57.0, null, "p" ] }, "how": { "fp32": "NVIDIA: “7+7 TOPs (FP32+INT32) and 57 Tensor TFLOPs” [nvidianews.nvidia.com]", "fp64": "Derived: FP32 ÷ 32 (this architecture's FP64 rate)", "fp16": "Derived from NVIDIA's headline figure, 57 TFLOPS FP16. On GeForce Turing, FP16 (FP32 accumulate) runs at half the FP16 (FP16 accumulate) rate", "int8": "Derived from NVIDIA's headline figure, 57 TFLOPS FP16. On GeForce Turing, INT8 runs at twice the FP16 (FP16 accumulate) rate", "int4": "Derived from NVIDIA's headline figure, 57 TFLOPS FP16. On GeForce Turing, INT4 runs at 4× the FP16 (FP16 accumulate) rate", "fp16a16": "NVIDIA: “7+7 TOPs (FP32+INT32) and 57 Tensor TFLOPs” (precision not stated; GeForce Turing headline figures are FP16) [nvidianews.nvidia.com]" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "tf32": "TF32 tensor cores arrived with Ampere", "bf16": "BF16 tensor cores arrived with Ampere", "fp8": "No FP8 tensor cores before Ada/Hopper (FP8 models run at FP16 speed)", "fp6": "No FP6 tensor cores before Blackwell", "fp4": "No FP4 tensor cores before Blackwell" }, "headline": "“7+7 TOPs (FP32+INT32) and 57 Tensor TFLOPs”", "anchor": "Derived from NVIDIA's headline figure, 57 TFLOPS FP16. ", "notes": "Wayback redirected the en-us spec page to en-eu (same NVIDIA content). The FP32 value comes from the press-release phrase '7+7 TOPs (FP32+INT32)'. GeForce news repeats '7+7 TOPs, 57 Tensor TFLOPs'. No whitepaper per-precision table exists for this card. The compare page lists 1.65 GHz boost, 1.47 GHz base, 175 W.", "sources": [ { "t": "nvidianews.nvidia.com — /news/with-great-power-comes-great-gaming-nvidia-launches-geforce-rtx-super-seri", "u": "https://nvidianews.nvidia.com/news/with-great-power-comes-great-gaming-nvidia-launches-geforce-rtx-super-series" }, { "t": "nvidia.com — /en-us/geforce/news/geforce-rtx-20-series-super-gpus/", "u": "https://www.nvidia.com/en-us/geforce/news/geforce-rtx-20-series-super-gpus/" }, { "t": "web.archive.org — /web/20191001023249/https://www.nvidia.com/en-eu/geforce/graphics-cards/rtx-2060", "u": "https://web.archive.org/web/20191001023249/https://www.nvidia.com/en-eu/geforce/graphics-cards/rtx-2060-super/" }, { "t": "nvidia.com — /en-us/geforce/graphics-cards/compare/", "u": "https://www.nvidia.com/en-us/geforce/graphics-cards/compare/" }, { "t": "en.wikipedia.org — /wiki/GeForce_20_series", "u": "https://en.wikipedia.org/wiki/GeForce_20_series" } ], "aka": null }, { "id": "rtx-2070-super", "name": "GeForce RTX 2070 SUPER", "short": "RTX 2070 SUPER", "seg": "geforce", "arch": "Turing", "archGroup": "Turing", "cls": "turing-geforce", "clsLabel": "Turing (GF)", "chip": "TU104", "date": "2019-07", "t": 2019.5, "status": null, "ff": "desktop PCIe card", "mem": 8.0, "memType": "GDDR6", "bw": 448.0, "tdp": 215.0, "sms": 40.0, "tc": 320.0, "cuda": 2560.0, "boost": 1770.0, "v": { "fp32": [ 9.1, null, "p" ], "fp64": [ 0.2844, null, "d" ], "fp16": [ 36.3, null, "p" ], "int8": [ 145.0, null, "p" ], "int4": [ 290.0, null, "p" ], "fp16a16": [ 72.5, null, "p" ] }, "how": { "fp32": "NVIDIA: “Table 10: Peak FP32 TFLOPS (non-Tensor) 9.1” [nvidia.com]", "fp64": "Derived: FP32 ÷ 32 (this architecture's FP64 rate)", "fp16": "NVIDIA: “Table 10: Peak FP16 Tensor TFLOPS with FP32 Accumulate 36.3” [nvidia.com]", "int8": "NVIDIA: “Table 10: Peak INT8 Tensor TOPS 145” [nvidia.com]", "int4": "NVIDIA: “Table 10: Peak INT4 Tensor TOPS 290” [nvidia.com]", "fp16a16": "NVIDIA: “Table 10: Peak FP16 Tensor TFLOPS with FP16 Accumulate 72.5” [nvidia.com]" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "tf32": "TF32 tensor cores arrived with Ampere", "bf16": "BF16 tensor cores arrived with Ampere", "fp8": "No FP8 tensor cores before Ada/Hopper (FP8 models run at FP16 speed)", "fp6": "No FP6 tensor cores before Blackwell", "fp4": "No FP4 tensor cores before Blackwell" }, "headline": "“9+9 TOPs (FP32+INT32) and 73 Tensor TFLOPs”", "anchor": "Derived from NVIDIA's published FP16 (FP16 accumulate) figure of 72.5 dense. ", "notes": "Whitepaper column is 'RTX 2070 Super Founders Edition'. NVIDIA's SUPER spec pages list a single spec, so FE = reference. Table 10 prints 'GPCs: 5 or 6', and its footnotes are numbered 4-6 although the cells reference 1-3 (WP typo). FP32 accumulate is half rate (36.3 vs 72.5). Press release FP32: '9+9 TOPs (FP32+INT32)'. The compare page lists base 1.61 GHz; the archived spec page lists 1605 MHz.", "sources": [ { "t": "nvidia.com — /content/PDF/nvidia-ampere-ga-102-gpu-architecture-whitepaper-v2.1.pdf", "u": "https://www.nvidia.com/content/PDF/nvidia-ampere-ga-102-gpu-architecture-whitepaper-v2.1.pdf" }, { "t": "nvidianews.nvidia.com — /news/with-great-power-comes-great-gaming-nvidia-launches-geforce-rtx-super-seri", "u": "https://nvidianews.nvidia.com/news/with-great-power-comes-great-gaming-nvidia-launches-geforce-rtx-super-series" }, { "t": "nvidia.com — /en-us/geforce/news/geforce-rtx-20-series-super-gpus/", "u": "https://www.nvidia.com/en-us/geforce/news/geforce-rtx-20-series-super-gpus/" }, { "t": "web.archive.org — /web/20191001022738/https://www.nvidia.com/en-eu/geforce/graphics-cards/rtx-2070", "u": "https://web.archive.org/web/20191001022738/https://www.nvidia.com/en-eu/geforce/graphics-cards/rtx-2070-super/" }, { "t": "nvidia.com — /en-us/geforce/graphics-cards/compare/", "u": "https://www.nvidia.com/en-us/geforce/graphics-cards/compare/" } ], "aka": null }, { "id": "rtx-2080-super", "name": "GeForce RTX 2080 SUPER", "short": "RTX 2080 SUPER", "seg": "geforce", "arch": "Turing", "archGroup": "Turing", "cls": "turing-geforce", "clsLabel": "Turing (GF)", "chip": "TU104", "date": "2019-07", "t": 2019.5, "status": null, "ff": "desktop PCIe card", "mem": 8.0, "memType": "GDDR6", "bw": 496.0, "tdp": 250.0, "sms": 48.0, "tc": 384.0, "cuda": 3072.0, "boost": 1815.0, "v": { "fp32": [ 11.2, null, "p" ], "fp64": [ 0.35, null, "d" ], "fp16": [ 44.6, null, "p" ], "int8": [ 178.4, null, "p" ], "int4": [ 356.8, null, "p" ], "fp16a16": [ 89.2, null, "p" ] }, "how": { "fp32": "NVIDIA: “Table 2: Peak FP32 TFLOPS (non-Tensor) 11.2” [nvidia.com]", "fp64": "Derived: FP32 ÷ 32 (this architecture's FP64 rate)", "fp16": "NVIDIA: “Table 2: Peak FP16 Tensor TFLOPS with FP32 Accumulate 44.6” [nvidia.com]", "int8": "NVIDIA: “Table 2: Peak INT8 Tensor TOPS 178.4” [nvidia.com]", "int4": "NVIDIA: “Table 2: Peak INT4 Tensor TOPS 356.8” [nvidia.com]", "fp16a16": "NVIDIA: “Table 2: Peak FP16 Tensor TFLOPS with FP16 Accumulate 89.2” [nvidia.com]" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "tf32": "TF32 tensor cores arrived with Ampere", "bf16": "BF16 tensor cores arrived with Ampere", "fp8": "No FP8 tensor cores before Ada/Hopper (FP8 models run at FP16 speed)", "fp6": "No FP6 tensor cores before Blackwell", "fp4": "No FP4 tensor cores before Blackwell" }, "headline": "“11+11 TOPs (FP32+INT32) and 89 Tensor TFLOPs”", "anchor": "Derived from NVIDIA's published FP16 (FP16 accumulate) figure of 89.2 dense. ", "notes": "Ada WP Table 3 'RTX 2080 Super' column matches exactly (1815 MHz, 11.2, 22.3, 89.2, 44.6, 178.4, 356.8, 496 GB/sec, TGP 250 W). GeForce news gives bandwidth as '496.1 GB/s'. ODDITY: GA102 WP Table 6 heads its Turing column 'TU102 SM (RTX 2080 Super)', but the RTX 2080 Super is TU104 (Tables 2 and 3 say TU104). The RTX 30 launch article has an image 'TURING - 1ST GENERATION RTX: 11 Shader-TFLOPS | 34 RT-TFLOPS | 89 Tensor-TFLOPS'. It names no card; it matches the 2080 SUPER. FP32 accumulate is half rate.", "sources": [ { "t": "nvidia.com — /content/PDF/nvidia-ampere-ga-102-gpu-architecture-whitepaper-v2.1.pdf", "u": "https://www.nvidia.com/content/PDF/nvidia-ampere-ga-102-gpu-architecture-whitepaper-v2.1.pdf" }, { "t": "images.nvidia.com — /aem-dam/Solutions/geforce/ada/nvidia-ada-gpu-architecture.pdf", "u": "https://images.nvidia.com/aem-dam/Solutions/geforce/ada/nvidia-ada-gpu-architecture.pdf" }, { "t": "nvidianews.nvidia.com — /news/with-great-power-comes-great-gaming-nvidia-launches-geforce-rtx-super-seri", "u": "https://nvidianews.nvidia.com/news/with-great-power-comes-great-gaming-nvidia-launches-geforce-rtx-super-series" }, { "t": "nvidia.com — /en-us/geforce/news/geforce-rtx-20-series-super-gpus/", "u": "https://www.nvidia.com/en-us/geforce/news/geforce-rtx-20-series-super-gpus/" }, { "t": "web.archive.org — /web/20191001022217/https://www.nvidia.com/en-eu/geforce/graphics-cards/rtx-2080", "u": "https://web.archive.org/web/20191001022217/https://www.nvidia.com/en-eu/geforce/graphics-cards/rtx-2080-super/" }, { "t": "nvidia.com — /en-us/geforce/news/introducing-rtx-30-series-graphics-cards/", "u": "https://www.nvidia.com/en-us/geforce/news/introducing-rtx-30-series-graphics-cards/" } ], "aka": null }, { "id": "rtx-2060", "name": "GeForce RTX 2060 6GB", "short": "RTX 2060 6GB", "seg": "geforce", "arch": "Turing", "archGroup": "Turing", "cls": "turing-geforce", "clsLabel": "Turing (GF)", "chip": "TU106", "date": "2019-01", "t": 2019.0, "status": null, "ff": "desktop PCIe card", "mem": 6.0, "memType": "GDDR6", "bw": 336.0, "tdp": 160.0, "sms": 30.0, "tc": 240.0, "cuda": 1920.0, "boost": 1680.0, "v": { "fp32": [ 6.4512, null, "d" ], "fp64": [ 0.2016, null, "d" ], "fp16": [ 26.0, null, "d" ], "int8": [ 104.0, null, "d" ], "int4": [ 208.0, null, "d" ], "fp16a16": [ 52.0, null, "p" ] }, "how": { "fp32": "Derived: 2 × 1,920 CUDA cores × 1,680 MHz boost clock", "fp64": "Derived: FP32 ÷ 32 (this architecture's FP64 rate)", "fp16": "Derived from NVIDIA's headline figure, 52 TFLOPS FP16. On GeForce Turing, FP16 (FP32 accumulate) runs at half the FP16 (FP16 accumulate) rate", "int8": "Derived from NVIDIA's headline figure, 52 TFLOPS FP16. On GeForce Turing, INT8 runs at twice the FP16 (FP16 accumulate) rate", "int4": "Derived from NVIDIA's headline figure, 52 TFLOPS FP16. On GeForce Turing, INT4 runs at 4× the FP16 (FP16 accumulate) rate", "fp16a16": "NVIDIA: “240 Tensor Cores that can deliver 52 teraflops of deep learning horsepower” (precision not stated; GeForce Turing headline figures are FP16) [nvidianews.nvidia.com]" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "tf32": "TF32 tensor cores arrived with Ampere", "bf16": "BF16 tensor cores arrived with Ampere", "fp8": "No FP8 tensor cores before Ada/Hopper (FP8 models run at FP16 speed)", "fp6": "No FP6 tensor cores before Blackwell", "fp4": "No FP4 tensor cores before Blackwell" }, "headline": "“240 Tensor Cores that can deliver 52 teraflops of deep learning horsepower”", "anchor": "Derived from NVIDIA's headline figure, 52 TFLOPS FP16. ", "notes": "Founders Edition runs at reference clock (1680 MHz); the archived page has one 'Product Spec' column. GeForce news repeats: '1,920 CUDA cores, 240 Tensor Cores that can deliver 52 teraflops of deep learning horsepower, 30 RT Cores ... 6 GB of the newest GDDR6 memory running at 14 Gbps, and a GPU boost clock of 1.68 GHz'. The current compare page lists 1.68 GHz boost, 1.37 GHz base, 160 W. The NVIDIA video codec matrix lists a 'GeForce RTX 2060 (TU104)' variant. No whitepaper per-precision table exists for this card.", "sources": [ { "t": "web.archive.org — /web/20190530195025/https://www.nvidia.com/en-us/geforce/graphics-cards/rtx-2060", "u": "https://web.archive.org/web/20190530195025/https://www.nvidia.com/en-us/geforce/graphics-cards/rtx-2060/" }, { "t": "nvidianews.nvidia.com — /news/nvidia-geforce-rtx-2060-is-here-next-gen-gaming-takes-off", "u": "https://nvidianews.nvidia.com/news/nvidia-geforce-rtx-2060-is-here-next-gen-gaming-takes-off" }, { "t": "nvidia.com — /en-us/geforce/news/nvidia-geforce-rtx-2060/", "u": "https://www.nvidia.com/en-us/geforce/news/nvidia-geforce-rtx-2060/" }, { "t": "nvidia.com — /en-us/geforce/graphics-cards/compare/", "u": "https://www.nvidia.com/en-us/geforce/graphics-cards/compare/" }, { "t": "en.wikipedia.org — /wiki/GeForce_20_series", "u": "https://en.wikipedia.org/wiki/GeForce_20_series" } ], "aka": null }, { "id": "titan-rtx", "name": "NVIDIA TITAN RTX", "short": "TITAN RTX", "seg": "geforce", "arch": "Turing", "archGroup": "Turing", "cls": "turing-pro", "clsLabel": "Turing (Quadro, Tesla, TITAN)", "chip": "TU102", "date": "2018-12", "t": 2018.9166666666667, "status": null, "ff": "dual-slot PCIe desktop card", "mem": 24.0, "memType": "GDDR6", "bw": 672.0, "tdp": 280.0, "sms": 72.0, "tc": 576.0, "cuda": 4608.0, "boost": 1770.0, "v": { "fp32": [ 16.3, null, "p" ], "fp64": [ 0.5094, null, "d" ], "fp16": [ 130.5, null, "p" ], "int8": [ 261.0, null, "p" ], "int4": [ 522.0, null, "p" ] }, "how": { "fp32": "NVIDIA: “Table 9: Peak FP32 TFLOPS (non-Tensor) 16.3” [nvidia.com]", "fp64": "Derived: FP32 ÷ 32 (this architecture's FP64 rate)", "fp16": "NVIDIA: “Table 9: Peak FP16 Tensor TFLOPS with FP32 Accumulate 130.5” [nvidia.com]", "int8": "NVIDIA: “Table 9: Peak INT8 Tensor TOPS 261” [nvidia.com]", "int4": "NVIDIA: “Table 9: Peak INT4 Tensor TOPS 522” [nvidia.com]" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "tf32": "TF32 tensor cores arrived with Ampere", "bf16": "BF16 tensor cores arrived with Ampere", "fp8": "No FP8 tensor cores before Ada/Hopper (FP8 models run at FP16 speed)", "fp6": "No FP6 tensor cores before Blackwell", "fp4": "No FP4 tensor cores before Blackwell" }, "headline": "“bringing 130 Tensor TFLOPs of performance, 576 tensor cores, and 24 GB of ultra-fast GDDR6 memory”", "anchor": "Derived from NVIDIA's published FP16 (FP16 accumulate) figure of 130.5 dense. ", "notes": "KEY: unlike the GeForce RTX 20 cards, TITAN RTX runs FP16 with FP32 accumulate at FULL rate. GA102 whitepaper Table 9 prints 130.5 for both FP16-accumulate and FP32-accumulate. The Turing whitepaper prints the same for the Quadro RTX 6000 (same full TU102, 1770 MHz). BF16 and TF32 are 'NA' (Turing). Table 9 lists 'Total Graphics Power (TGP) 280 Watts'; the NVIDIA page lists 280 W TDP. Branded NVIDIA TITAN, not GeForce. Live NVIDIA page now redirects to the RTX 6000 page, so the archived copy is used.", "sources": [ { "t": "nvidia.com — /content/PDF/nvidia-ampere-ga-102-gpu-architecture-whitepaper-v2.1.pdf", "u": "https://www.nvidia.com/content/PDF/nvidia-ampere-ga-102-gpu-architecture-whitepaper-v2.1.pdf" }, { "t": "web.archive.org — /web/20200531230334/https://www.nvidia.com/en-us/deep-learning-ai/products/titan", "u": "https://web.archive.org/web/20200531230334/https://www.nvidia.com/en-us/deep-learning-ai/products/titan-rtx/" }, { "t": "nvidianews.nvidia.com — /news/nvidia-reveals-the-titan-of-turing-titan-rtx", "u": "https://nvidianews.nvidia.com/news/nvidia-reveals-the-titan-of-turing-titan-rtx" } ], "aka": null }, { "id": "rtx-2070", "name": "GeForce RTX 2070", "short": "RTX 2070", "seg": "geforce", "arch": "Turing", "archGroup": "Turing", "cls": "turing-geforce", "clsLabel": "Turing (GF)", "chip": "TU106", "date": "2018-10", "t": 2018.75, "status": null, "ff": "desktop PCIe card", "mem": 8.0, "memType": "GDDR6", "bw": 448.0, "tdp": 175.0, "sms": 36.0, "tc": 288.0, "cuda": 2304.0, "boost": 1620.0, "v": { "fp32": [ 7.5, null, "p" ], "fp64": [ 0.2344, null, "d" ], "fp16": [ 29.9, null, "p" ], "int8": [ 119.4, null, "p" ], "int4": [ 238.9, null, "p" ], "fp16a16": [ 59.7, null, "p" ] }, "how": { "fp32": "NVIDIA: “Table 6: Peak FP32 TFLOPS (Reference / Founders Edition) 7.5 / 7.9” [images.nvidia.com]", "fp64": "Derived: FP32 ÷ 32 (this architecture's FP64 rate)", "fp16": "NVIDIA: “Table 6: Peak FP16 Tensor TFLOPS with FP32 Accumulate (Reference/Founders Edition) 29.9 / 31.5” [images.nvidia.com]", "int8": "NVIDIA: “Table 6: Peak INT8 Tensor TOPS (Reference / Founders Edition) 119.4 / 126” [images.nvidia.com]", "int4": "NVIDIA: “Table 6: Peak INT4 Tensor TOPS (Reference / Founders Edition) 238.9 / 252.1” [images.nvidia.com]", "fp16a16": "NVIDIA: “Table 6: Peak FP16 Tensor TFLOPS with FP16 Accumulate (Reference/Founders Edition) 59.7 / 63” [images.nvidia.com]" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "tf32": "TF32 tensor cores arrived with Ampere", "bf16": "BF16 tensor cores arrived with Ampere", "fp8": "No FP8 tensor cores before Ada/Hopper (FP8 models run at FP16 speed)", "fp6": "No FP6 tensor cores before Blackwell", "fp4": "No FP4 tensor cores before Blackwell" }, "headline": null, "anchor": "Derived from NVIDIA's published FP16 (FP16 accumulate) figure of 59.7 dense. ", "notes": "GeForce half-rate FP32 accumulate is visible: FP16-with-FP32-accumulate (29.9) is exactly half of FP16-with-FP16-accumulate (59.7). CONFLICT: the current NVIDIA compare page lists the RTX 2070 at Boost 1.71 GHz and 185 W, which are the Founders Edition (OC) values, without labeling them FE; reference is 1620 MHz / 175 W. RTX-OPS 42T / 45T; 6 Giga Rays/s.", "sources": [ { "t": "images.nvidia.com — /aem-dam/en-zz/Solutions/design-visualization/technologies/turing-architecture/N", "u": "https://images.nvidia.com/aem-dam/en-zz/Solutions/design-visualization/technologies/turing-architecture/NVIDIA-Turing-Architecture-Whitepaper.pdf" }, { "t": "web.archive.org — /web/20190602085749/https://www.nvidia.com/en-us/geforce/graphics-cards/rtx-2070", "u": "https://web.archive.org/web/20190602085749/https://www.nvidia.com/en-us/geforce/graphics-cards/rtx-2070/" }, { "t": "nvidianews.nvidia.com — /news/10-years-in-the-making-nvidia-brings-real-time-ray-tracing-to-gamers-with-", "u": "https://nvidianews.nvidia.com/news/10-years-in-the-making-nvidia-brings-real-time-ray-tracing-to-gamers-with-geforce-rtx" }, { "t": "nvidia.com — /en-us/geforce/graphics-cards/compare/", "u": "https://www.nvidia.com/en-us/geforce/graphics-cards/compare/" } ], "aka": null }, { "id": "rtx-2080", "name": "GeForce RTX 2080", "short": "RTX 2080", "seg": "geforce", "arch": "Turing", "archGroup": "Turing", "cls": "turing-geforce", "clsLabel": "Turing (GF)", "chip": "TU104", "date": "2018-09", "t": 2018.6666666666667, "status": null, "ff": "desktop PCIe card", "mem": 8.0, "memType": "GDDR6", "bw": 448.0, "tdp": 215.0, "sms": 46.0, "tc": 368.0, "cuda": 2944.0, "boost": 1710.0, "v": { "fp32": [ 10.0, null, "p" ], "fp64": [ 0.3125, null, "d" ], "fp16": [ 40.3, null, "p" ], "int8": [ 161.1, null, "p" ], "int4": [ 322.2, null, "p" ], "fp16a16": [ 80.5, null, "p" ] }, "how": { "fp32": "NVIDIA: “Table 4: Peak FP32 TFLOPS (Reference / Founders Edition) 10 / 10.6” [images.nvidia.com]", "fp64": "Derived: FP32 ÷ 32 (this architecture's FP64 rate)", "fp16": "NVIDIA: “Table 4: Peak FP16 Tensor TFLOPS with FP32 Accumulate (Reference/Founders Edition) 40.3 / 42.4” [images.nvidia.com]", "int8": "NVIDIA: “Table 4: Peak INT8 Tensor TOPS (Reference / Founders Edition) 161.1 / 169.6” [images.nvidia.com]", "int4": "NVIDIA: “Table 4: Peak INT4 Tensor TOPS (Reference / Founders Edition) 322.2 / 339.1” [images.nvidia.com]", "fp16a16": "NVIDIA: “Table 4: Peak FP16 Tensor TFLOPS with FP16 Accumulate (Reference/Founders Edition) 80.5 / 84.8” [images.nvidia.com]" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "tf32": "TF32 tensor cores arrived with Ampere", "bf16": "BF16 tensor cores arrived with Ampere", "fp8": "No FP8 tensor cores before Ada/Hopper (FP8 models run at FP16 speed)", "fp6": "No FP6 tensor cores before Blackwell", "fp4": "No FP4 tensor cores before Blackwell" }, "headline": null, "anchor": "Derived from NVIDIA's published FP16 (FP16 accumulate) figure of 80.5 dense. ", "notes": "GA102 WP Table 2 'GeForce RTX 2080 Founders Edition' column repeats the FE figures exactly: boost 1800, FP32 10.6, FP16 21.2, FP16-acc16 84.8, FP16-acc32 42.4, INT8 169.6, INT4 339.1, TGP 225 W. There is no conflict between the two whitepapers. FP32 accumulate is half rate. CONFLICT: the current compare page lists 1.8 GHz / 225 W (FE values) without labeling them FE. RTX-OPS 57T / 60T; 8 Giga Rays/s.", "sources": [ { "t": "images.nvidia.com — /aem-dam/en-zz/Solutions/design-visualization/technologies/turing-architecture/N", "u": "https://images.nvidia.com/aem-dam/en-zz/Solutions/design-visualization/technologies/turing-architecture/NVIDIA-Turing-Architecture-Whitepaper.pdf" }, { "t": "nvidia.com — /content/PDF/nvidia-ampere-ga-102-gpu-architecture-whitepaper-v2.1.pdf", "u": "https://www.nvidia.com/content/PDF/nvidia-ampere-ga-102-gpu-architecture-whitepaper-v2.1.pdf" }, { "t": "web.archive.org — /web/20190602085749/https://www.nvidia.com/en-us/geforce/graphics-cards/rtx-2080", "u": "https://web.archive.org/web/20190602085749/https://www.nvidia.com/en-us/geforce/graphics-cards/rtx-2080/" }, { "t": "nvidianews.nvidia.com — /news/10-years-in-the-making-nvidia-brings-real-time-ray-tracing-to-gamers-with-", "u": "https://nvidianews.nvidia.com/news/10-years-in-the-making-nvidia-brings-real-time-ray-tracing-to-gamers-with-geforce-rtx" }, { "t": "nvidia.com — /en-us/geforce/graphics-cards/compare/", "u": "https://www.nvidia.com/en-us/geforce/graphics-cards/compare/" } ], "aka": null }, { "id": "rtx-2080-ti", "name": "GeForce RTX 2080 Ti", "short": "RTX 2080 Ti", "seg": "geforce", "arch": "Turing", "archGroup": "Turing", "cls": "turing-geforce", "clsLabel": "Turing (GF)", "chip": "TU102", "date": "2018-09", "t": 2018.6666666666667, "status": null, "ff": "desktop PCIe card", "mem": 11.0, "memType": "GDDR6", "bw": 616.0, "tdp": 250.0, "sms": 68.0, "tc": 544.0, "cuda": 4352.0, "boost": 1545.0, "v": { "fp32": [ 13.4, null, "p" ], "fp64": [ 0.4188, null, "d" ], "fp16": [ 53.8, null, "p" ], "int8": [ 215.2, null, "p" ], "int4": [ 430.3, null, "p" ], "fp16a16": [ 107.6, null, "p" ] }, "how": { "fp32": "NVIDIA: “Table 1: Peak FP32 TFLOPS (Reference/Founders Edition) 13.4 / 14.2” [images.nvidia.com]", "fp64": "Derived: FP32 ÷ 32 (this architecture's FP64 rate)", "fp16": "NVIDIA: “Table 1: Peak FP16 Tensor TFLOPS with FP32 Accumulate (Reference/Founders Edition) 53.8 / 56.9” [images.nvidia.com]", "int8": "NVIDIA: “Table 1: Peak INT8 Tensor TOPS (Reference/Founders Edition) 215.2 / 227.7” [images.nvidia.com]", "int4": "NVIDIA: “Table 1: Peak INT4 Tensor TOPS (Reference/Founders Edition) 430.3 / 455.4” [images.nvidia.com]", "fp16a16": "NVIDIA: “Table 1: Peak FP16 Tensor TFLOPS with FP16 Accumulate (Reference/Founders Edition) 107.6 / 113.8” [images.nvidia.com]" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "tf32": "TF32 tensor cores arrived with Ampere", "bf16": "BF16 tensor cores arrived with Ampere", "fp8": "No FP8 tensor cores before Ada/Hopper (FP8 models run at FP16 speed)", "fp6": "No FP6 tensor cores before Blackwell", "fp4": "No FP4 tensor cores before Blackwell" }, "headline": null, "anchor": "Derived from NVIDIA's published FP16 (FP16 accumulate) figure of 107.6 dense. ", "notes": "Turing WP intro (p.2) for the 2080 Ti Founders Edition gives '113.8 Tensor TFLOPS', with footnote 2 defining Tensor TFLOPS as 'FP16 matrix math with FP16 accumulation'. Ada WP Tables 1-2 list the 2080 Ti at 1635 MHz (the FE clock, not labeled FE) with FE figures: FP32 14.2, FP16 28.5, FP16-acc16 113.8, FP16-acc32 56.9, INT8 227.7, INT4 455.4, TGP 260 W. These agree with the Turing WP FE column. CONFLICT: the current compare page lists 1.64 GHz / 260 W, the FE values, without labeling them FE. FP32 accumulate is half rate (53.8 vs 107.6). Per the TU102 note, the FP64 rate is 1/32 of FP32; no FP64 TFLOPS is printed. RTX-OPS 76 / 78; 10 Giga Rays/s.", "sources": [ { "t": "images.nvidia.com — /aem-dam/en-zz/Solutions/design-visualization/technologies/turing-architecture/N", "u": "https://images.nvidia.com/aem-dam/en-zz/Solutions/design-visualization/technologies/turing-architecture/NVIDIA-Turing-Architecture-Whitepaper.pdf" }, { "t": "images.nvidia.com — /aem-dam/Solutions/geforce/ada/nvidia-ada-gpu-architecture.pdf", "u": "https://images.nvidia.com/aem-dam/Solutions/geforce/ada/nvidia-ada-gpu-architecture.pdf" }, { "t": "web.archive.org — /web/20190530195025/https://www.nvidia.com/en-us/geforce/graphics-cards/rtx-2080", "u": "https://web.archive.org/web/20190530195025/https://www.nvidia.com/en-us/geforce/graphics-cards/rtx-2080-ti/" }, { "t": "nvidianews.nvidia.com — /news/10-years-in-the-making-nvidia-brings-real-time-ray-tracing-to-gamers-with-", "u": "https://nvidianews.nvidia.com/news/10-years-in-the-making-nvidia-brings-real-time-ray-tracing-to-gamers-with-geforce-rtx" }, { "t": "nvidia.com — /en-us/geforce/graphics-cards/compare/", "u": "https://www.nvidia.com/en-us/geforce/graphics-cards/compare/" } ], "aka": null }, { "id": "titan-v", "name": "NVIDIA TITAN V", "short": "TITAN V", "seg": "geforce", "arch": "Volta", "archGroup": "Volta", "cls": "volta", "clsLabel": "Volta (GV100)", "chip": "GV100", "date": "2017-12", "t": 2017.9166666666667, "status": null, "ff": "dual-slot PCIe desktop card", "mem": 12.0, "memType": "HBM2", "bw": 652.8, "tdp": 250.0, "sms": 80.0, "tc": 640.0, "cuda": 5120.0, "boost": 1455.0, "v": { "fp32": [ 14.8992, null, "d" ], "fp64": [ 7.4496, null, "d" ], "fp16": [ 110.0, null, "d" ] }, "how": { "fp32": "Derived: 2 × 5,120 CUDA cores × 1,455 MHz boost clock", "fp64": "Derived: FP32 ÷ 2 (this architecture's FP64 rate)", "fp16": "Derived from NVIDIA's headline figure, 110 TFLOPS FP16. On Volta, FP16 (FP32 accumulate) runs at the same rate as FP16 (FP16 accumulate)" }, "na": { "fp64tc": "No FP64 tensor cores (only big data-centre chips such as GA100, GH100 and GB100 have them)", "tf32": "TF32 tensor cores arrived with Ampere", "bf16": "BF16 tensor cores arrived with Ampere", "fp8": "No FP8 tensor cores before Ada/Hopper (FP8 models run at FP16 speed)", "fp6": "No FP6 tensor cores before Blackwell", "fp4": "No FP4 tensor cores before Blackwell", "int8": "No INT8 tensor cores on this architecture", "int4": "No INT4 tensor cores on this architecture" }, "headline": "“110 DEEP LEARNING TeraFLOPS”", "anchor": "Derived from NVIDIA's headline figure, 110 TFLOPS FP16. ", "notes": "Branded NVIDIA TITAN, not GeForce; grouped here as a consumer desktop card. The live NVIDIA TITAN V page now redirects to the RTX 6000 page, so the 2018 archived copy is used. NVIDIA publishes only the single 110 TFLOPS deep-learning figure; it prints no FP64/FP32/FP16 TFLOPS for this card. The 110 figure cannot be reproduced from NVIDIA's own 640 Tensor Cores x 1455 MHz boost (see open_questions). Base clock 1200 MHz. The 32 GB 'TITAN V CEO Edition' is a separate product and not covered.", "sources": [ { "t": "web.archive.org — /web/20180603202718/https://www.nvidia.com/en-us/titan/titan-v/", "u": "https://web.archive.org/web/20180603202718/https://www.nvidia.com/en-us/titan/titan-v/" }, { "t": "nvidianews.nvidia.com — /news/nvidia-titan-v-transforms-the-pc-into-ai-supercomputer", "u": "https://nvidianews.nvidia.com/news/nvidia-titan-v-transforms-the-pc-into-ai-supercomputer" }, { "t": "hothardware.com — /news/nvidia-volta-titan-v-12gb-hbm2-110-tflops", "u": "https://hothardware.com/news/nvidia-volta-titan-v-12gb-hbm2-110-tflops" } ], "aka": null } ] }